6
FN4324.2
December 27, 2004
complete its cycle. Figure 4 shows this operation with an
overload condition. Note that the inductor current increases
to over 15A during the C
SS
charging interval and causes an
overcurrent trip. The converter dissipates very little power
with this method. The measured input power for the
conditions of Figure 4 is 2.5W.
The overcurrent function will trip at a peak inductor current
(I
PEAK)
determined by:
where I
OCSET
is the internal OCSET current source (200µA
- typical). The OC trip point varies mainly due to the
MOSFETs r
DS(ON)
variations. To avoid overcurrent tripping
in the normal operating load range, find the R
OCSET
resistor
from the equation above with:
1. The maximum r
DS(ON)
at the highest junction temperature.
2. The minimum I
OCSET
from the specification table.
3. Determine ,
where ∆I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R
OCSET
to smooth the voltage across R
OCSET
in the
presence of switching noise on the input voltage.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C
IN
and C
O
each represent numerous physical capacitors.
Locate the HIP6012 within 3 inches of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and
source connections from the HIP6012 must be sized to
handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
SS
close to the SS pin because the internal current source is
only 10µA. Provide local V
CC
decoupling between VCC and
GND pins. Locate the capacitor, C
BOOT
as close as practical
to the BOOT and PHASE pins.
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V
E/A
) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
IN
at the
PHASE node. The PWM wave is smoothed by the output filter
(L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) Divided by the
peak-to-peak oscillator voltage ∆V
OSC
.
I
PEAK
I
OCSET
R
OCSET
•
r
DS ON()
---------------------------------------------------=
I
PEAK
for I
PEAK
I
OUT MAX()
∆I()2⁄+>
PGND
L
O
C
O
LGATE
UGATE
PHASE
Q1
Q2
D2
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
V
IN
V
OUT
RETURN
HIP6012
C
IN
LOAD
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+12V
HIP6012
SS
GND
VCC
BOOT
D1
L
O
C
O
V
OUT
LOAD
Q1
Q2
PHASE
+V
IN
C
BOOT
C
VCC
C
SS
HIP6012
