NLV74HC4060ADR2G

© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 10
1 Publication Order Number:
MC74HC4060A/D
MC74HC4060A
14-Stage Binary Ripple
Counter With Oscillator
High−Performance Silicon−Gate CMOS
The MC74HC4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 master−slave flip−flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC
circuit connected externally. The output of each flip−flop feeds the
next and the frequency at each output is half of that of the preceding
one. The state of the counter advances on the negative−going edge of
the Osc In. The active−high Reset is asynchronous and disables the
oscillator to allow very low power consumption during stand−by
operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
Q4
7
Q5
5
Q6
4
Q7
6
Q8
14
Q9
13
Q10
15
Q12
1
Q13
2
Q14
3
Osc In
11
Reset
12
Pin 16 = V
CC
Pin 8 = GND
Osc Out 1 Osc Out 2
910
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
HC4060AG
AWLYWW
HC40
60A
ALYWG
G
1
16
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Clock Reset Output State
X
L
L
H
No Change
Advance to Next State
All Outputs Are Low
SOIC−16 TSSOP−16
PIN ASSIGNMENT
16−Lead Package (Top View)
1516 14 13 12 11 10
21 34567
V
CC
9
8
Q10 Q8 Q9 Reset Osc In
Osc
Out 1
Osc
Out 2
Q12 Q13 Q14 Q6 Q5 Q7 Q4
GND
MC74HC4060A
www.onsemi.com
2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature Range – 65 to + 150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.5* 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature Range, All Package Types –55 +125
_C
t
r
, t
f
Input Rise/Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at
2.0 V by driving Pin 11 with an external clock source.
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbo
l
Parameter Condition
V
CC
V
Guaranteed Limit
Unit
−55 to 25°C 85°C 125°C
V
IH
Minimum High−Level Input Voltage V
out
= 0.1V or V
CC
−0.1V
|I
out
| 20mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
V
IL
Maximum Low−Level Input Voltage V
out
= 0.1V or V
CC
− 0.1V
|I
out
| 20mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
OH
Minimum High−Level Output Voltage
(Q4−Q10, Q12−Q14)
V
in
= V
IH
or V
IL
|I
out
| 20mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
=V
IH
or V
IL
|I
out
| 2.4mA
|I
out
| 4.0mA
|I
out
| 5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low−Level Output Voltage
(Q4−Q10, Q12−Q14)
V
in
= V
IH
or V
IL
|I
out
| 20mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| 2.4mA
|I
out
| 4.0mA
|I
out
| 5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC4060A
www.onsemi.com
3
DC CHARACTERISTICS (Voltages Referenced to GND) (continued)
Symbol Unit
Guaranteed Limit
V
CC
V
ConditionParameter
Symbol Unit
125°C85°C−55 to 25°C
V
CC
V
ConditionParameter
V
OH
Minimum High−Level Output Voltage
(Osc Out 1, Osc Out 2)
V
in
= V
CC
or GND
|I
out
| 20mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
=V
CC
or GND |I
out
| 0.7mA
|I
out
| 1.0mA
|I
out
| 1.3mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low−Level Output Voltage
(Osc Out 1, Osc Out 2)
V
in
= V
CC
or GND
|I
out
| 20mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
=V
CC
or GND |I
out
| 0.7mA
|I
out
| 1.0mA
|I
out
| 1.3mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0mA
6.0 4 40 160
mA
AC CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbo
l
Parameter
V
CC
V
Guaranteed Limit
Unit
−55 to 25°C 85°C 125°C
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
10
30
50
9.0
14
28
45
8.0
12
25
40
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
2.0
3.0
4.5
6.0
300
180
60
51
375
200
75
64
450
250
90
75
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
2.0
3.0
4.5
6.0
500
350
250
200
750
450
275
220
1000
600
300
250
ns
t
PHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
195
75
39
33
245
100
49
42
300
125
61
53
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
2.0
3.0
4.5
6.0
75
60
15
13
95
75
19
16
125
95
24
20
ns
AC CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns) − continued
Symbo
l
Parameter
V
CC
V
Guaranteed Limit
Unit
−55 to 25°C 85°C 125°C
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
* For T
A
= 25°C and C
L
= 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
V
CC
= 2.0 V: t
P
= [93.7 + 59.3 (n−1)] ns V
CC
= 4.5 V: t
P
= [30.25 + 14.6 (n−1)] ns
V
CC
= 3.0 V: t
P
= [61.5+ 34.4 (n−1)] ns V
CC
= 6.0 V: t
P
= [24.4 + 12 (n−1)] ns
C
PD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, V
CC
= 5.0 V
pF
35
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.

NLV74HC4060ADR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter ICs 14-STGE BINRY RIPPLE COUN
Lifecycle:
New from this manufacturer.
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