NLV74HC4060ADR2G

MC74HC4060A
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TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (T
A
= 25°C; Input = Pin 11, Output = Pin 10)
Type
Positive Reactance (Pierce)
Input Resistance, R
in
60MW Minimum
Output Impedance, Z
out
(4.5V Supply)
200W (See Text)
Input Capacitance, C
in
5pF Typical
Output Capacitance, C
out
7pF Typical
Series Capacitance, C
a
5pF Typical
Open Loop Voltage Gain with Output at Full Swing, α 3Vdc Supply
4Vdc Supply
5Vdc Supply
6Vdc Supply
5.0 Expected Minimum
4.0 Expected Minimum
3.3 Expected Minimum
3.1 Expected Minimum
PIERCE CRYSTAL OSCILLATOR DESIGN
Figure 8. Equivalent Crystal Networks
R
S
L
S
C
S
Re Xe 212121
C
O
Value are supplied by crystal manufacturer (parallel resonant crystal).
Figure 9. Series Equivalent Crystal Load Figure 10. Parasitic Capacitances of the Amplifier
Z
load
-jX
Co
-jX
C2
R
-jX
C
-jX
Cs
jX
Ls
R
S
R
load
X
load
NOTE: C = C1 + C
in
and R = R1 + R
out
. C
o
is considered as part of
the load. C
a
and R
f
typically have minimal effect below 2MHz.
C
in
C
out
C
a
Values are listed in Table 1.
MC74HC4060A
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8
DESIGN PROCEDURES
The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional
impedance elements should be considered: C
out
and C
a
of the amp, feedback resistor R
f
, and amplifier phase shift error from
180°C.
Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.
Z
e
+
* jX
C
o
(R
s
) jX
L
s
* jX
C
s
)
* jX
C
o
) R
s
) jX
L
s
* jX
C
s
+ R
e
) jX
e
Reactance jX
e
should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency.
The maximum R
s
for the crystal should be used in the equation.
Step 2: Determine β, the attenuation, of the feedback network. For a closed-loop gain of 2,A
ν
β = 2,β = 2/A
ν
where A
ν
is
the gain of the HC4060A amplifier.
Step 3: Determine the manufacturers loading capacitance. For example: A manufacturer may specify an external load
capacitance of 32pF at the required frequency.
Step 4: Determine the required Q of the system, and calculate R
load
, For example, a manufacturer specifies a crystal Q of
100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then R
load
= (2πf
o
L
S
/Q) − R
s
where L
s
and R
s
are
crystal parameters.
Step 5: Simultaneously solve, using a computer,
b +
X
C
@ X
C2
R @ R
e
) X
C2
(X
e
* X
C
)
( Eq
1
(with feedback phase shift = 180°)
X
e
+ X
C2
) X
C
)
R
e
X
C2
R
+ X
C
load
( Eq
2
(where the loading capacitor is an external load, not including C
o
)
R
load
+
RX
C
o
X
C2
[(X
C
) X
C2
)(X
C
) X
C
o
) * X
C
(X
C
) X
C
o
) X
C2
)]
X
2
C2
(X
C
) X
C
o
)
2
) R
2
(X
C
) X
C
o
) X
C2
)
2
( Eq
3
Here R = R
out
+ R1. R
out
is amp output resistance, R1 is Z. The C corresponding to X
C
is given by C = C1 + C
in
.
Alternately, pick a value for R1 (i.e, let R1 = R
S
). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that
Q = 2πf
o
L
s
/(R
s
+ R
load
) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.
CHOOSING R1
Power is dissipated in the effective series resistance of the
crystal. The drive level specified by the crystal manufacturer
is the maximum stress that a crystal can withstand without
damage or excessive shift in frequency. R1 limits the drive
level.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at Osc Out 2 (Pin 9). The frequency
should increase very slightly as the dc supply voltage is
increased. An overdriven crystal will decrease in frequency
or become unstable with an increase in supply voltage. The
operating supply voltage must be reduced or R1 must be
increased in value if the overdriven condition exists. The
user should note that the oscillator start-up time is
proportional to the value of R1.
SELECTING R
f
The feedback resistor, R
f
, typically ranges up to 20MW. R
f
determines the gain and bandwidth of the amplifier. Proper
bandwidth insures oscillation at the correct frequency plus
roll-off to minimize gain at undesirable frequencies, such as
the first overtone. R
f
must be large enough so as to not affect
the phase of the feedback network in an appreciable manner.
ACKNOWLEDGEMENTS AND RECOMMENDED
REFERENCES
The following publications were used in preparing this
data sheet and are hereby acknowledged and recommended
for reading:
Technical Note TN-24, Statek Corp.
Technical Note TN-7, Statek Corp.
D. Babin, “Designing Crystal Oscillators”, Machine
Design, March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.
ALSO RECOMMENDED FOR READING:
E. Hafner, “The Piezoelectric Crystal Unit-Definitions
and Method of Measurement”, Proc. IEEE, Vol. 57, No. 2,
Feb., 1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro-Technology, June, 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.
MC74HC4060A
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9
Clock
Reset
Q4
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
Figure 11. Timing Diagram

NLV74HC4060ADR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter ICs 14-STGE BINRY RIPPLE COUN
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