74HC237_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 14 January 2013 9 of 16
NXP Semiconductors
74HC237-Q100
3-to-8 line decoder, demultiplexer with address latches
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Propagation enable inputs (E1) to output (Yn) and output transition time
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E1 input
Yn output
V
M
t
PHL
t
THL
t
TLH
t
PLH
V
M
90 %90 %
10 %10 %
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. The data input (An) to latch enable input (LE) set-up times, latch enable input (LE) to data input (An) hold
times and latch enable input (LE) pulse width
t
su
t
h
LE input
V
M
V
M
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t
h
t
su
t
W
An input
transparant transparantlatched latched
Table 8. Measurement points
Type Input Output
V
M
V
M
74HC237-Q100 0.5V
CC
0.5V
CC
