Rev C 7/13/15 4 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK
GENERATOR
87002-02 DATA SHEET
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3 SEL2 SEL1 SEL0 Q0, Q1
0000 ÷8
0001 ÷8
0010 ÷8
0011 ÷16
0100 ÷16
0101 ÷16
0110 ÷32
0111 ÷32
1000 ÷64
1001 ÷128
1010 ÷4
1011 ÷4
1100 ÷8
1101 ÷2
1110 ÷4
1111 ÷2
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK
GENERATOR
5 Rev C 7/13/15
87002-02 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= V
DDA
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 4B. Power Supply DC Characteristics, V
DD
= V
DDA
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 100 mA
I
DDA
Analog Supply Current 16 mA
I
DDO
Output Supply Current 6mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 2.375 2.5 2.625 V
V
DDA
Analog Supply Voltage 2.375 2.5 2.625 V
V
DDO
Output Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 96 mA
I
DDA
Analog Supply Current 15 mA
I
DDO
Output Supply Current 6mA
Rev C 7/13/15 6 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK
GENERATOR
87002-02 DATA SHEET
Table 4C. LVCMOS/LVTTL DC Characteristics, V
DD
= V
DDA
= V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
NOTE 1: Outputs terminated with 50 to V
DDO
/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams.
Table 4D. Differential DC Characteristics, V
DD
= V
DDA
= V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage
V
DD
= 3.3V 2 V
DD
+ 0.3 V
V
DD
= 2.5V 1.7 V
DD
+ 0.3 V
V
IL
Input Low Voltage
V
DD
= 3.3V -0.3 0.8 V
V
DD
= 2.5V -0.3 0.7 V
I
IH
Input High Current
FB_IN,
SEL[0:3], MR
V
DD
= V
IN
= 3.465V or 2.625V 150 µA
PLL_SEL V
DD
= V
IN
= 3.465V or 2.625V 5 µA
I
IL
Input Low Current
FB_IN,
SEL[0:3], MR
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
-5 µA
PLL_SEL
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
-150 µA
V
OH
Output High Voltage; NOTE 1
V
DDO
= 3.465V 2.6 V
V
DDO
= 2.625V 1.8 V
V
OL
Output Low Voltage; NOTE 1 V
DDO
= 3.465V or 2.625V 0.5 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK V
DD
= V
IN
= 3.465V or 2.625V 150 µA
nCLK V
DD
= V
IN
= 3.465V or 2.625V 150 µA
I
IL
Input Low Current
CLK V
DD
= 3.465V or 2.625V, V
IN
= 0V -5 µA
nCLK V
DD
= 3.465V or 2.625V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
GND + 0.5 V
DD
– 0.85 V

87002AG-02LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer PLL Based Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
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