1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK
GENERATOR
15 Rev C 7/13/15
87002-02 DATA SHEET
Revision History Sheet
Rev Table Page Description of Change Date
B
T2
T8
2
10
11
12
14
Pin Characteristics Table - added C
PD
specs.
Added Recommendations for Unused Input and Output Pins section.
Updated Differential Clock Input Interface section.
Added Schematic Layout
Ordering Information Table - added Lead-Free marking.
4/29/08
C
T5A, T5B
T5B
T8
7
7
10
14
Added thermal note.
2.5V AC Characteristics Table - due to datasheet conversion on April 29, 2008, corrected
typo for static phase offset spec from -650 to -65.
Updated Wiring the Differential Levels to Accept Single-ended Levels section.
Ordering Information Table - deleted “ICS” prefix from the Part/Order Number column.
Updated header/footer of datasheet.
8/9/10
C
T8 14 Ordering Information - removed leaded devices.
Updated data sheet format.
7/13/15