1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK
GENERATOR
7 Rev C 7/13/15
87002-02 DATA SHEET
AC Electrical Characteristics
Table 5A. AC Characteristics, V
DD
= V
DDA
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V
DD
= V
DDA
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 15.625 250 MHz
t
PD
Propagation Delay; NOTE 1
PLL_SEL = 0V, f 250MHz,
Qx ÷ 2
4.8 5.8 ns
t(Ø) Static Phase Offset; NOTE 2, 4
PLL_SEL = 3.3V,
f
REF
167MHz, Qx ÷ 1
-160 -10 140 ps
tsk(o) Output Skew; NOTE 3, 4 PLL_SEL = 0V 40 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f
OUT
> 40MHz 45 ps
t
L
PLL Lock Time 1ms
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 400 800 ps
odc Output Duty Cycle 40 60 %
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 15.625 250 MHz
t
PD
Propagation Delay; NOTE 1
PLL_SEL = 0V, f 250MHz,
Qx ÷ 2
4.9 6.7 ns
t(Ø) Static Phase Offset; NOTE 2, 4
PLL_SEL = 2.5V,
f
REF
167MHz, Qx ÷ 1
-240 -65 110 ps
tsk(o) Output Skew; NOTE 3, 4 PLL_SEL = 0V 35 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f
OUT
> 40MHz 45 ps
t
L
PLL Lock Time 1ms
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 400 700 ps
odc Output Duty Cycle 44 56 %
