1997 Oct 21 24
Philips Semiconductors Product specification
I
2
C-bus controller
PCF8584
12 I
2
C-BUS TIMING SPECIFICATIONS
All the timing limits are valid within the operating supply voltage and ambient temperature range; V
DD
=5V±10%;
T
amb
= −40 to +85 °C; and refer to V
IL
and V
IH
with an input voltage of V
SS
to V
DD.
13 PARALLEL INTERFACE TIMING
All the timing limits are valid within the operating supply voltage and ambient temperature range: V
DD
=5V±10%;
T
amb
= −40 to +85 °C; and refer to V
IL
and V
IH
with an input voltage of V
SS
to V
DD
. C
L
= 100 pF; R
L
= 1.5 kΩ
(connected to V
DD
) for open-drain and high-impedance outputs, where applicable (for measurement purposes only).
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
f
SCL
SCL clock frequency −− 100 kHz
t
SW
tolerable spike width on bus −− 100 ns
t
BUF
bus free time 4.7 −−µs
t
SU;STA
START condition set-up time 4.7 −−µs
t
HD;STA
START condition hold time 4.0 −−µs
t
LOW
SCL LOW time 4.7 −−µs
t
HIGH
SCL HIGH time 4.0 −−µs
t
r
SCL and SDA rise time −− 1.0 µs
t
f
SCL and SDA fall time −− 0.3 µs
t
SU;DAT
data set-up time 250 −−ns
t
HD;DAT
data hold time 0 −−ns
t
VD;DAT
SCL LOW to data out valid −− 3.4 µs
t
SU;STO
STOP condition set-up time 4.0 −−µs
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
t
r
clock rise time see Fig.14 −− 6ns
t
f
clock fall time see Fig.14 −− 6ns
t
CLK
input clock period
(50% ±5% duty factor)
see Fig.14 83 − 333 ns
t
CLRL
CS set-up to RD LOW see Fig.16 and note 1 20 −−ns
t
CLWL
CS set-up to WR LOW see Fig.15 and note 1 20 −−ns
t
RHCH
CS hold from RD HIGH see Fig.16 0 −−ns
t
WHCH
CS hold from WR HIGH see Fig.15 0 −−ns
t
AVWL
A0 set-up to WR LOW see Fig.15 10 −−ns
t
AVRL
A0 set-up to RD LOW see Fig.16 10 −−ns
t
WHAI
A0 hold from WR HIGH see Fig.15 20 −−ns
t
RHAI
A0 hold from RD HIGH see Fig.16 10 −−ns
t
WLWH
WR pulse width see Fig.15 230 − 1000 ns
t
RLRH
RD pulse width see Fig.16 230 − 1000 ns
t
DVWH
data set-up before WR HIGH see Fig.15 150 −−ns
t
RLDV
data valid after RD LOW see Fig.16 − 160 180 ns
t
WHDI
data hold after WR HIGH see Fig.15 20 −−ns
t
RHDF
data bus floating after RD
HIGH
see Fig.16 −− 150 ns
