LTC6601-2
12
66012f
PIN FUNCTIONS
IN1
+
, IN2
+
, IN4
+
(Pins 2, 1, 20): Input to a trimmed 100Ω,
200Ω, 400Ω resistor which feeds a noninverting summing
node. Can accept an input signal, be fl oated or tied to OUT
–
.
For best performance, stray capacitance should be kept as
low as possible by keeping printed circuit connections as
short and direct as possible. If necessary, strip back the
surrounding ground plane away from these pins.
BIAS (Pin 3): Input to a three-state comparator whose
three states allow the user to tailor amplifi er power. The
pin impedance appears as a 150k resistor whose default
open-circuit potential is 1.15V with respect to the V
–
power
supply. If BIAS is driven to within 0.4V of the V
–
supply, the
amplifi er is placed into a low power shutdown, consum-
ing typically 450µA. When BIAS is fl oated, the amplifi er
operates in its low power active state. Forcing the pin 2.3V
above V
–
places the part into the high performance active
state. See Applications Information for more detail.
IN1
–
, IN2
–
, IN4
–
(Pins 4, 5, 6): Input to a trimmed 100Ω,
200Ω, 400Ω resistor which feeds an inverting summing
node. Can accept an input signal, be fl oated or tied to
OUT
+
. For best performance, it is highly recommended
that stray capacitance be kept to as low as possible by
keeping printed circuit connections as short and direct
as possible, and if necessary, stripping back nearby sur-
rounding ground plane away from these pins.
C1, C2 (Pins 7, 8): Input to a trimmed 16.1pF, 33.3pF
capacitor which feeds a noninverting summing node.
Typically, either fl oat or tie to OUT
–
. If either of these
pins is tied to a low impedance source other than OUT
–
,
a resistance of at least 25Ω should be placed in series.
For best performance, it is highly recommended that stray
capacitance be kept to as low as possible by keeping printed
circuit connections as short and direct as possible, and
if necessary, stripping back nearby surrounding ground
plane away from these pins.
C3, C4 (Pins 9, 10): Input to a trimmed 10.55pF, 21.1pF
capacitor which feeds the amplifi er inverting summing
node. Typically, either fl oat or tie to OUT
+
. For best per-
formance, it is highly recommended that stray capacitance
be kept to as low as possible by keeping printed circuit
connections as short and direct as possible, and if nec-
essary, stripping back nearby surrounding ground plane
away from these pins.
OUT
+
, OUT
–
(Pins 11, 15): Output Pins. Besides driving
the internal feedback network, each pin can drive an ad-
ditional 50Ω to ground with typical short-circuit current
limiting of ±65mA. Capacitive loading of these pins should
be minimized by resistively decoupling the outputs from
the load with at least 25Ω.
V
OCM
(Pin 12): Output Common Mode Reference Voltage.
The voltage on V
OCM
sets the output common mode voltage
level (which is defi ned as the average of the voltages on
the OUT
+
and OUT
–
pins). The V
OCM
pin is the midpoint
of an internal resistive voltage divider between the sup-
plies, developing a (default) mid-supply voltage potential
to maximize output signal swing. The V
OCM
pin can be
overdriven by an external voltage reference capable of
driving the input impedance presented by the V
OCM
pin.
The V
OCM
pin has an input resistance of approximately 7k
to a mid-supply potential. It should be bypassed with a
high quality ceramic bypass capacitor (for instance of X7R
dielectric) of at least 0.01F, (unless using symmetrical
split supplies, then connect directly to a low impedance,
low noise ground plane) to minimize common mode noise
from being converted to differential noise by impedance
mismatches both externally and internally to the IC.
(Refer to the Block Diagram)
