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LTC6601CUF-2#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
LTC6601-2
4
66012f
DC ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. V
+
= 3V, V
–
= 0V, V
INCM
= V
OCM
= mid-supply, BIAS tied to V
+
or fl oating,
I
LOAD
= 0, R
BAL
= 100k. The fi lter is confi gured for a gain of 1 unless otherwise noted. V
S
is defi ned as (V
+
– V
–
). V
OUTCM
is defi ned as
(V
OUT
+
+ V
OUT
–
)/2. V
INCM
is defi ned as (V
INP
+ V
INM
)/2. V
OUTDIFF
is defi ned as (V
OUT
+
– V
OUT
–
). V
INDIFF
is defi ned as (V
INP
– V
INM
). See
Figure 1.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OUT
Output Voltage, High, Either Output Pin
(Note 11)
V
S
= 3V, I
L
= 0mA, BIAS Pin Floating
V
S
= 3V, I
L
= –5mA, BIAS Pin Floating
V
S
= 3V, I
L
= –20mA, BIAS Pin Floating
V
S
= 5V, I
L
= 0mA, BIAS Pin Floating
V
S
= 5V, I
L
= –5mA, BIAS Pin Floating
V
S
= 5V, I
L
= –20mA, BIAS Pin Floating
l
l
l
l
l
l
240
290
470
370
430
650
450
525
850
675
775
1100
mV
mV
mV
mV
mV
mV
V
S
= 3V, I
L
= 0mA BIAS = V
+
V
S
= 3V, I
L
= –5mA BIAS = V
+
V
S
= 3V, I
L
= –20mA BIAS = V
+
V
S
= 5V, I
L
= 0mA BIAS = V
+
V
S
= 5V, I
L
= –5mA BIAS = V
+
V
S
= 5V, I
L
= –20mA BIAS = V
+
l
l
l
l
l
l
245
285
415
350
390
550
450
525
750
625
700
1000
mV
mV
mV
mV
mV
mV
Output Voltage, Low, Either Output Pin
(Note 11)
V
S
= 3V, I
L
= 0mA, BIAS Pin Floating
V
S
= 3V, I
L
= 5mA, BIAS Pin Floating
V
S
= 3V, I
L
= 20mA, BIAS Pin Floating
V
S
= 5V, I
L
= 0mA, BIAS Pin Floating
V
S
= 5V, I
L
= 5mA, BIAS Pin Floating
V
S
= 5V, I
L
= 20mA, BIAS Pin Floating
l
l
l
l
l
l
110
120
170
150
170
225
200
225
300
270
300
400
mV
mV
mV
mV
mV
mV
V
S
= 3V, I
L
= 0mA BIAS = V
+
V
S
= 3V, I
L
= 5mA BIAS = V
+
V
S
= 3V, I
L
= 20mA BIAS = V
+
V
S
= 5V, I
L
= 0mA BIAS = V
+
V
S
= 5V, I
L
= 5mA BIAS = V
+
V
S
= 5V, I
L
= 20mA BIAS = V
+
l
l
l
l
l
l
120
135
195
175
200
270
225
250
350
325
360
475
mV
mV
mV
mV
mV
mV
I
SC
Output Short-Circuit Current,
Either Output Pin (Note 12)
V
S
= 3V
V
S
= 5V
l
l
±45
±60
±65
±90
mA
mA
V
S
Supply Voltage Range
l
2.7 5.25 V
I
S
Supply Current, BIAS Pin Floating V
S
= 2.7V
V
S
= 3V
V
S
= 5V
l
l
l
15.8
16
16.7
23
23.5
24.5
mA
mA
mA
Supply Current, BIAS Pin Tied to V
+
V
S
= 2.7V
V
S
= 3V
V
S
= 5V
l
l
l
32
32.2
33
41
41.5
43
mA
mA
mA
I
SHDN
Supply Current, BIAS Pin Tied to V
–
V
S
= 2.7V
V
S
= 3V
V
S
= 5V
l
l
l
0.4
0.45
0.65
1
1.1
1.8
mA
mA
mA
V
BIASSD
BIAS Input Pin Range for Shutdown V
S
= 2.7V to 5V
l
V
–
V
–
+ 0.4 V
V
BIASLP
(Note 13) BIAS Input for Low Power Operation V
S
= 2.7V to 5V
l
V
–
+ 1.0 V
–
+ 1.5 V
V
BIASHP
BIAS Input for High Performance Operation V
S
= 2.7V to 5V
l
V
–
+ 2.3 V
+
V
R
BIAS
BIAS Input Resistance V
S
= 2.7V to 5V
l
100 150 200 kΩ
V
BIAS
BIAS Float Voltage V
S
= 2.7V to 5V
l
V
–
+ 1.05 V
–
+
1.15
V
–
+ 1.25 V
t
ON
Turn-On Time V
S
= 3V, V
SHDN
= 0.25V to 3V 400 ns
t
OFF
Turn-Off Time V
S
= 3V, V
SHDN
= 3V to 0.25V 400 ns
LTC6601-2
5
66012f
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. V
+
= 3V, V
–
= 0V, V
INCM
= V
OCM
= mid-supply, V
BIAS
is tied to V
+
or
fl oating, unless otherwise noted. (See Figure 2 for the AC test confi guration.) V
S
is defi ned as (V
+
– V
–
). V
OUTCM
is defi ned as (V
OUT
+
+
V
OUT
–
)/2. V
ICM
is defi ned as (V
INP
+ V
INM
)/2. V
OUTDIFF
is defi ned as (V
OUT
+
– V
OUT
–
). V
INDIFF
is defi ned as (V
INP
– V
INM
).
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
GAIN Filter Gain, See Figure 2,
BIAS Pin Floating (Remaining AC
Measurements Relative to 1MHz)
ΔV
IN
= ±0.25V, f
TEST
= DC (Note 14)
V
IN
= 600mV
P-P
, f
TEST
= 1MHz
V
IN
= 600mV
P-P
, f
TEST
= 2MHz
V
IN
= 600mV
P-P
, f
TEST
= 5MHz
V
IN
= 600mV
P-P
, f
TEST
= 10MHz
V
IN
= 600mV
P-P
, f
TEST
= 14.45MHz
V
IN
= 600mV
P-P
, f
TEST
= 20MHz
V
IN
= 600mV
P-P
, f
TEST
= 50MHz
l
l
l
l
l
l
l
l
–0.25
–0.08
–0.01
–0.54
–3.00
–7.55
–23.55
±0.05
0
0.02
0.11
–0.34
–2.50
–6.55
–21.55
0.25
0.12
0.23
–0.14
–2.00
–5.55
–19.55
dB
dB
dB
dB
dB
dB
dB
dB
PHASE Filter Phase, See Figure 2,
BIAS Pin Floating
ΔV
IN
= ±0.25V, f
TEST
= DC
V
IN
= 600mV
P-P
, f
TEST
= 1MHz
V
IN
= 600mV
P-P
, f
TEST
= 2MHz
V
IN
= 600mV
P-P
, f
TEST
= 5MHz
V
IN
= 600mV
P-P
, f
TEST
= 10MHz
V
IN
= 600mV
P-P
, f
TEST
= 14.45MHz
V
IN
= 600mV
P-P
, f
TEST
= 20MHz
V
IN
= 600mV
P-P
, f
TEST
= 50MHz
l
l
l
l
l
l
l
l
–6.0
–12.5
–31.8
–70.1
–103.5
–130.7
0
–5.5
–11.3
–29.3
–65.2
–97.5
–125.1
–173.6
–4.8
–10.1
–26.8
–60.1
–91.5
–120.7
Deg
Deg
Deg
Deg
Deg
Deg
Deg
Deg
NOISE Output Noise, See Figure 2,
BIAS Pin Floating
BW = 100MHz
BW = 20MHz
154
135
µV
RMS
µV
RMS
SNR BIAS Pin Floating BW = 100MHz
BW = 20MHz
73
74
dB
dB
Distortion V
IN
= 2V
P-P
, 10MHz, BIAS Pin Floating HD2, Single-Ended Input
HD3, Single-Ended Input
HD2, Differential Input
HD3, Differential Input
–60
–79
–65
–77
dBc
dBc
dBc
dBc
f
O
TC Cutoff Frequency Temperature Coeffi cient –120 ppm/°C
GAIN Filter Gain, See Figure 2,
BIAS Pin Tied to V
+
,
AC Gain Measurements Relative to 1MHz
ΔV
IN
= ±0.25V, f
TEST
= DC (Note 14)
V
IN
= 600mV
P-P
, f
TEST
= 1MHz
V
IN
= 600mV
P-P
, f
TEST
= 2MHz
V
IN
= 600mV
P-P
, f
TEST
= 5MHz
V
IN
= 600mV
P-P
, f
TEST
= 10MHz
V
IN
= 600mV
P-P
, f
TEST
= 14.45MHz
V
IN
= 600mV
P-P
, f
TEST
= 20MHz
V
IN
= 600mV
P-P
, f
TEST
= 50MHz
l
l
l
l
l
l
l
l
–0.25
–0.08
–0.01
–0.54
–2.75
–7.14
–23.70
±0.05
0
0.02
0.11
–0.34
–2.35
–6.24
–21.70
0.25
0.12
0.23
–0.14
–1.95
–5.34
–19.70
dB
dB
dB
dB
dB
dB
dB
dB
PHASE Filter Phase, See Figure 2,
BIAS Pin Tied to V
+
ΔV
IN
= ±0.25V, f
TEST
= DC
V
IN
= 600mV
P-P
, f
TEST
= 1MHz
V
IN
= 600mV
P-P
, f
TEST
= 2MHz
V
IN
= 600mV
P-P
, f
TEST
= 5MHz
V
IN
= 600mV
P-P
, f
TEST
= 10MHz
V
IN
= 600mV
P-P
, f
TEST
= 14.45MHz
V
IN
= 600mV
P-P
, f
TEST
= 20MHz
V
IN
= 600mV
P-P
, f
TEST
= 50MHz
l
l
l
l
l
l
l
l
–6.0
–12.2
–31.2
–68.8
–101.5
–128.4
0
–5.4
–11
–28.7
–63.8
–95.5
–123.4
–169.3
–4.8
–9.8
–26.2
–58.8
–89.5
–118.4
Deg
Deg
Deg
Deg
Deg
Deg
Deg
Deg
NOISE Wide Band Output Noise, 14.45MHz Cutoff,
BIAS Pin Tied to V
+
BW = 100MHz
BW = 20MHz
108
97
µV
RMS
µV
RMS
SNR BIAS Pin Tied to V
+
BW = 100MHz
BW = 20MHz
76
77
dB
dB
DISTORTION V
IN
= 2V
P-P
, 10MHz, BIAS Pin Tied to V
+
HD2, Single-Ended Input
HD3, Single-Ended Input
HD2, Differential Input
HD3, Differential Input
–67.5
–90
–70
–90
dBc
dBc
dBc
dBc
f
O
TC Cutoff Frequency Temperature Coeffi cient –120 ppm/°C
LTC6601-2
6
66012f
Note 1: Stresses beyond those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. Exposure to any
Absolute Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Note 2: All pins are protected by steering diodes to either supply. If any
pin is driven beyond the part’s supply voltage, the excess input current
(current in excess of what it takes to drive that pin to the supply rail)
should be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefi nitely. Long-term application of output currents in excess of the
Absolute Maximum Ratings may impair the life of the device.
Note 4: The LTC6601C/LTC6601I are guaranteed functional over the
operating temperature range –40°C to 85°C.
Note 5: The LTC6601C is guaranteed to meet specifi ed performance from
0°C to 70°C. The LTC6601C is designed, characterized, and expected
to meet specifi ed performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LTC6601I is guaranteed to meet
specifi ed performance from –40°C to 85°C.
Note 6: Output referred voltage offset is a function of the low frequency
gain of the LTC6601. To determine output referred voltage offset, or output
voltage offset drift, multiply this specifi cation by the noise gain (1 + GAIN).
See Applications Information for more details.
Note 7: Input bias current is defi ned as the average of the currents
fl owing into the noninverting and inverting inputs of the internal amplifi er
and is calculated from measurements made at the pins of the IC. Input
offset current is defi ned as the difference of the currents fl owing into the
noninverting and inverting inputs of the internal amplifi er and is calculated
from measurements made at the pins of the IC.
Note 8: Input common mode range is tested using the test circuit of
Figure 1 by measuring the differential DC gain with V
ICM
= mid-supply, and
with V
ICM
at the input common mode range limits listed in the Electrical
Characteristics table, verifying the differential gain has not deviated from
the mid-supply common mode input case by more than 1%, and the
common mode offset (V
OCMOS
) has not deviated from the mid-supply
common mode offset by more than ±20mV.
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by measuring the differential DC gain with V
OCM
=
mid-supply, and again with a voltage set on the V
OCM
pin at the Electrical
Characteristics table limits, checking the differential gain has not deviated
from the mid-supply common mode input case by more than 1%, and that
the common mode offset (V
OCMOS
) has not deviated by more than ±20mV
from the mid-supply case.
Note 9: Input CMRR is defi ned as the ratio of the change in the input
common mode voltage at the amplifi er input to the change in differential
input referred voltage offset. Output CMRR is defi ned as the ratio of the
change in the voltage at the V
OCM
pin to the change in differential input
referred voltage offset.
Note 10: Power supply rejection (PSRR) is defi ned as the ratio of the
change in supply voltage to the change in differential input referred voltage
offset. Common mode power supply rejection (PSRRCM) is defi ned as the
ratio of the change in supply voltage to the change in the common mode
offset, V
OUTCM
/V
OCM
.
Note 11: Output swings are measured as differences between the output
and the respective power supply rail.
Note 12: Extended operation with the output shorted may cause junction
temperatures to exceed the 150°C limit and is not recommended.
Note 13: Floating the BIAS pin will reliably place the part into the half-
power mode. The pin does not have to be driven. Care should be taken,
however, to prevent external leakage currents in or out of this pin from
pulling the pin into an undesired state.
Note 14: The variable contact resistance of the high speed test equipment
limits the accuracy of this test. These parameters only show a typical
value, or conservative minimum and maximum value.
ELECTRICAL CHARACTERISTICS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

LTC6601CUF-2#TRPBF

Mfr. #:
Buy LTC6601CUF-2#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Differential Amplifiers Low Power, Low Distortion, 0.5% Tolerance, Pin Configurable Filter/Amplifier
Lifecycle:
New from this manufacturer.
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