71V67703S75BQGI Datasheet 71V67703S85PFGI, 71V67903S85PFG, 71V67703S75PFG | P7-P9

6.42

7

IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

1234567

A V

DDQ

A

6

A

4

ADSP

A

8

A

16

V

DDQ

B NC CS

0

(4)

A

3

ADSC

A

9

A

18

NC

C A

7

A

2

V

DD

A

13

A

17

NC

D I/O

8

NC V

SS

NC V

SS

I/O

P1

NC

E NC I/O

9

V

SS

CE

V

SS

NC I/O

7

F V

DDQ

NC V

SS

OE

V

SS

I/O

6

V

DDQ

G NC I/O

10

ADVBW

2

NC I/O

5

H I/O

11

NC V

SS

GW

V

SS

I/O

4

NC

J V

DDQ

V

DD

NC

V

DD

NC V

DD

V

DDQ

K NC I/O

12

V

SS

CLK V

SS

NC I/O

3

L I/O

13

NC NC

BW

1

I/O

2

NC

M V

DDQ

I/O

14

V

SS

BWE

V

SS

NC V

DDQ

N

I/O

15

NC V

SS

A

1

V

SS

I/O

1

NC

P NC I/O

P2

V

SS

A

0

V

SS

NC I/O

0

R NC A

5

LBO

V

DD

NCA

12

V

SS

T

NC A

10

A

15

NC A

14

A

11

ZZ

U V

DDQ

DNU

(3)

DNU

(3)

DNU

(3)

DNU

(3)

DNU

(3)

V

DDQ

5309 drw 02d

NC

V

SS

V

SS

,

(1)

(2)

Pin Configuration – 512K x 18, 119 BGA

Pin Configuration – 256K x 36, 119 BGA

Top View

NOTES:

1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. T7 can be left unconnected and the device will always remain in active mode.

3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.

4. On future 18M devices CS

0

will be removed, B2 will be used for address expansion.

1234567

A V

DDQ

A

6

A

4

ADSP

A

8

A

16

V

DDQ

B NC

CS

0

(4)

A

3

ADSC

A

9

NC

C A

7

A

2

V

DD

A

12

A

15

NC

D

I/O

16

I/O

P3

V

SS

NC V

SS

I/O

P2

I/O

15

E I/O

17

I/O

18

V

SS

CE

V

SS

I/O

13

I/O

14

F

V

DDQ

I/O

19

V

SS

OE

V

SS

I/O

12

V

DDQ

G

I/O

20

I/O

21

BW

3

ADV BW

2

I/O

11

I/O

10

H

I/O

22

I/O

23

V

SS

GW

V

SS

I/O

9

I/O

8

J

V

DDQ

V

DD

NC V

DD

NC

V

DD

V

DDQ

K I/O

24

I/O

26

V

SS

CLK V

SS

I/O

6

I/O

7

L

I/O

25

I/O

27

BW

4

NC

BW

1

I/O

4

I/O

5

M V

DDQ

I/O

28

V

SS

BWE

V

SS

I/O

3

V

DDQ

N I/O

29

I/O

30

V

SS

A

1

V

SS

I/O

2

I/O

1

P I/O

31

I/O

P4

V

SS

A

0

V

SS

I/O

0

I/O

P1

R NC A

5

LBO

V

DD

NCA

13

T

NC NC A

10

A

11

A

14

NC ZZ

U V

DDQ

DNU

(3)

DNU

(3)

DNU

(3)

DNU

(3)

DNU

(3)

V

DDQ

NC

V

SS

5309 drw 02c

A17

(1)

(2)

6.428

IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration – 512K x 18, 165 fBGA

Pin Configuration – 256K x 36, 165 fBGA

1234567891011

ANC

(3)

A

7

CE BW

3

BW

2

CS

1

BWE ADSC ADV

A

8

NC

BNC A

6

CS

0

BW

4

BW

1

CLK

GW OE ADSP

A

9

NC

(3)

CI/O

P3

NC V

DDQ

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDQ

NC I/O

P2

DI/O

17

I/O

16

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

15

I/O

14

EI/O

19

I/O

18

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

13

I/O

12

FI/O

21

I/O

20

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

11

I/O

10

GI/O

23

I/O

22

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

9

I/O

8

HV

SS

(1)

NC NC V

DD

V

SS

V

SS

V

SS

V

DD

NC NC ZZ

(2)

JI/O

25

I/O

24

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

7

I/O

6

KI/O

27

I/O

26

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

5

I/O

4

LI/O

29

I/O

28

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

3

I/O

2

MI/O

31

I/O

30

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

1

I/O

0

NI/O

P4

NC V

DDQ

V

SS

NC NC

(3)

NC V

SS

V

DDQ

NC I/O

P1

PNCNC

(3)

A

5

A

2

DNU

(4)

A

1

DNU

(4)

A

10

A

13

A

14

A

17

R

LBO

NC

(3)

A

4

A

3

DNU

(4)

A

0

DNU

(4)

A

11

A

12

A

15

A

16

5309tbl 17a

1234567891011

ANC

(3)

A

7

CE BW

2

NC

CS

1

BWE ADSC AD V

A

8

A

10

BNC A

6

CS

0

NC

BW

1

CLK

GW OE ADSP

A

9

NC

(3)

CNC NCV

DDQ

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDQ

NC I/O

P1

DNC I/O

8

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

NC I/O

7

ENC I/O

9

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

NC I/O

6

FNCI/O

10

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

NC I/O

5

GNC I/O

11

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

NC I/O

4

HV

SS

(1)

NC NC V

DD

V

SS

V

SS

V

SS

V

DD

NC NC ZZ

(2)

JI/O

12

NC V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

3

NC

KI/O

13

NC V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

2

NC

LI/O

14

NC V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

1

NC

MI/O

15

NC V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

0

NC

NI/O

P2

NC V

DDQ

V

SS

NC NC

(3)

NC V

SS

V

DDQ

NC NC

PNC NC

(3)

A

5

A

2

DNU

(4)

A

1

DNU

(4)

A

11

A

14

A

15

A

18

R

LBO

NC

(3)

A

4

A

3

DNU

(4)

A

0

DNU

(4)

A

12

A

13

A

16

A

17

5309 tbl 17b

NOTES:

1. H1 does not have to be directly connected to VSS, as long as the input voltage is < VIL.

2. H11 can be left unconnected and the device will always remain in active mode.

3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.

4. DNU= Do not use; these signals can either be left unconnected or tied to Vss.

6.42

9

IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

1

2

3

4

20 30 50 100 200

Δt

CD

(Typical, ns)

Capacitance (pF)

80

5

6

5309 drw 05

,

V

DDQ

/2

50Ω

I/O

Z

0

=50Ω

5309 drw 03

,

Symbol Parameter Test Conditions Min. Max. Unit

|I

LI

| Input Leakage Current V

DD

= Max., V

IN

= 0V to V

DD

___

5µA

|I

LI

|

LBO Input Leakage Current

(1)

V

DD

= Max., V

IN

= 0V to V

DD

___

30 µA

|I

LO

| Output Leakage Current V

OUT

= 0V to V

CC

___

5µA

V

OL

Output Low Voltage I

OL

= +8mA, V

DD

= Min.

___

0.4 V

V

OH

Output High Voltage I

OH

= -8mA, V

DD

= Min. 2.4

___

V

5309 tbl 08

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(1)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(VDD = 3.3V ± 5%)

Figure 2. Lumped Capacitive Load, Typical Derating

Figure 1. AC Test Load

AC Test Load

AC Test Conditions

(VDDQ = 3.3V/2.5V)

NOTE:

1. The LBO pin will be internally pulled to V

DD if it is not actively driven in the application and the ZZ in will be internally pulled to VSS if not actively driven.

NOTES:

1. All values are maximum guaranteed values.

2. At f = f

MAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

Symbol Parameter Test Conditions

7.5ns 8ns 8.5ns

Unit

Com'l Ind Com'l Ind Com'l Ind

I

DD

Operating Power Supply Current Device Selected, Outputs Open, V

DD

= Max.,

V

DDQ

= Max., V

IN

> V

IH

or < V

IL

, f = f

MAX

(2 )

265 285 210 230 190 210

mA

I

SB1

CMOS Standby Power Supply Current Device Deselected, Outputs Open, V

DD

= Max.,

V

DDQ

= Max., V

IN

> V

HD

or < V

LD

, f = 0

(2,3)

50 70 50 70 50 70

mA

I

SB2

Clock Running Power Supply Current Device Deselected, Outputs Open, V

DD

= Max.,

V

DDQ

= Max., V

IN

> V

HD

or < V

LD

, f = f

MAX

(2,.3)

145 165 140 160 135 155

mA

I

ZZ

Full Sleep Mode Supply Current ZZ > V

HD,

V

DD

= Max. 50 70 50 70 50 70 mA

5309 tbl 09

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

0 to

3V

2ns

1.5V

See Figure 1

5309 tbl 10

71V67703S75BQGI

71V67703S75BQGI

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