22
LTC1923
1923f
APPLICATIO S I FOR ATIO
WUUU
Noise and Slew Rate Control
One disadvantage of switching regulators is that the
switching creates wideband harmonic energy. The high
frequency content can pose problems to associated cir-
cuitry. To combat this issue, the LTC1923 offers a pin
called R
SLEW
that controls the slew rate of the output drive
waveforms. Slowing down the transition interval reduces
the harmonic frequency content by spreading out the
energy over a longer time period. The additional transition
time causes some efficiency loss (on the order of 2% to
3%) but significantly improves the high frequency noise
reflected onto the input supply.
Slew rate control is engaged by placing a resistor from
R
SLEW
to AGND. If slew rate control is not desired, the R
SLEW
pin should be tied to V
DD
allowing the output drivers to
transition at their fastest rate. The resistor value should be
set between 10k (fastest transition) and 300k (slowest tran-
sition). This provides about a 10:1 slew rate range to op-
timize noise performance. The “break-before-make” time
may need to be increased if slew control is implemented,
especially for slower transition rates. Adjustment can be
done by increasing the value of R
T
(C
T
can be reduced to
maintain the same frequency of operation), to ensure that
the bridge MOSFETs receive nonoverlapping drive.
Power MOSFET Selection
Four external MOSFETs must be selected for use with the
LTC1923; a pair of N-channel MOSFETs for the bottom of
the bridge and a pair of P-channel MOSFETs for the top
diagonals of the bridge. The MOSFETs should be selected
for their R
DS(ON)
, gate charge and maximum V
DS,
V
GS
ratings. A maximum V
DS
rating of 20V is more than
sufficient for 5V and 12V bridge applications, but as
mentioned in the High Voltage Application section, a 12V
maximum V
GS
rating is insufficient and higher voltage
MOSFETs must be selected. There is a trade-off between
R
DS(ON)
and gate charge. The R
DS(ON)
affects the conduc-
tion losses (I
TEC
2
• R
DS(ON)
), while gate charge is a
dominant contributor to switching losses. A higher R
DS(ON)
MOSFET typically has a smaller gate capacitance and thus
requires less current to charge the gate for the same
BV
DSS
. For 1A TEC applications, the Si9801DY or Si9928DY
complimentary N- and P-channel MOSFETs provide a
good trade-off between switching and conduction losses.
Above this TEC current level the MOSFETs selected should
have lower R
DS(ON)
to maintain the high end efficiency.
Efficiency Considerations
Unlike typical voltage regulators, where the output voltage
is fixed, independent of load current, the output voltage of
this regulator changes with load current. This is because
the TEC appears resistive and the current through the TEC
sets the voltage. The output power of the regulator is
defined as:
P
OUT
= I
TEC
2
• R
TEC
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%.
Often it is useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most significant improvement. Efficiency can
be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
For this application, the main efficiency concern is typi-
cally at the high end of output power. A higher power loss
translates into a greater system temperature rise, result-
ing in the need for heat sinking, increasing both the system
size and cost.
There are three main sources which usually account for
most of the losses in the application shown on the front
page of the data sheet: Input supply current, MOSFET
switching losses and I
2
R losses.
1) The input supply current is comprised of the quiescent
current draw from the LTC1658, LTC2053, LTC1923 and
any additional circuitry added. The total maximum supply
current for these devices is on the order of 5mA, which
gives a total power dissipation of 25mW. This power loss
is independent of TEC current.
2) The MOSFET driver current results from switching the
gate capacitance of the power MOSFETs. Each time a gate
is switched from low to high to low again, a packet of
charge dQ moves from V
DD
to ground. The gate charging
current, I
GATECHG
= 2 • f • (Q
P
+ Q
N
), where Q
P
and Q
N
are
