15
LTC1923
1923f
The terms containing the fixed resistance values are the
loading errors introduced by the input impedance of the
differential amplifier. A common mode voltage error is
also introduced since the addition of R
TE1
and R
TE2
change
the fully differential nature of the amplifier. In order to
minimize these errors select R
TE1
and R
TE2
to be 10k or
less. The above equation reduces to:
V
R
R
TECOOLER
TE
TE
≅+
125
1
2
.
The Higher Voltage Applications section shows a fully
differential means to increase the clamp voltage.
This will similarly alter the heating and cooling direction
thresholds by the same factor, increasing the thresholds
to
(R
TE1
and R
TE2
are assumed to be ≤10k)
:
DIRH mV
R
R
DIRL mV
R
R
TE
TE
TE
TE
=+
=+
50 1
50 1
1
2
1
2
–
The output voltage on the VTEC pin, V
VTEC
, will be reduced
by the same ratio:
V
V
R
R
VTEC
TECOOLER
TE
TE
=
+1
1
2
Oscillator Frequency
The oscillator determines the switching frequency and the
fundamental positioning of all harmonics. The switching
frequency also affects the size of the inductor that needs
to be selected for a given inductor ripple current (as
opposed to TEC ripple current which is a function of both
the filter inductor and capacitor). A higher switching
frequency allows a smaller valued inductor for a given
ripple current. The oscillator is a triangle wave design. A
current defined by external resistor R
T
is used to charge
and discharge the capacitor C
T
. The charge and discharge
rates are equal. The selection of high quality external
components (5% or better multilayer NPO or X7R ceramic
capacitor) is important to ensure oscillator frequency
stability.
The frequency of oscillation is determined by:
f
OSC(kHz)
= 750 • 10
6
/[R
T
(kΩ) • C
T
(pF)]
The LTC1923 can run at frequencies up to 1MHz. The value
selected for R
T
will also affect the delay time between one
side of the full bridge turning off and the opposite side
turning on. This time is also known as the “break-before-
make” time. The typical value of 10kΩ will produce a 90ns
“break-before-make” time. For higher frequency applica-
tions, a smaller value of R
T
may be required to reduce this
delay time. For applications where significant slew rate
limiting or external gate driver chips are used, a higher
value for R
T
may necessary, increasing the dead time. The
“break-before-make” time can be approximately calcu-
lated by:
t
DELAY
= R
T
(kΩ) • 5.75 • 10
–9
+ 35ns
Phase-Locked Loop
The LTC1923 has an internal voltage-controlled oscillator
(VCO) and phase detector comprising a phase-locked
loop. This allows the oscillator to be synchronized with
another oscillator by slaving it to a master through the
SDSYNC pin. The part can also be designated as the
master by pulling the PLLLPF pin high to V
DD
. This will
result in the part toggling the SDSYNC pin at its set
oscillator frequency. This signal can then be used to
synchronize additional oscillators.
When being slaved to another oscillator, the frequency
should be set 20% to 30% lower than the target frequency.
The frequency lock range is approximately ±50%.
The phase detector is an edge sensitive digital type, which
provides zero degrees phase shift between the external
and internal oscillators. This detector will not lock up on
input frequencies close to the harmonics of the VCO center
frequency. The VCO hold-in range is equal to the capture
range dfH = dfC = ±0.5f
O
.
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLLPF pin. A simplified block
diagram is shown in Figure 8.
OPERATIO
U
