LTC1929CG-PG#PBF Datasheet LTC1929CG-PG#PBF, LTC1929IG-PG#PBF, LTC1929CG#TRPBF | P10-P12

LTC1929/LTC1929-PG

OPERATIO

(Refer to Functional Diagram)

Main Control Loop

The LTC1929 uses a constant frequency, current mode

step-down architecture with inherent current sharing.

During normal operation, the top MOSFET is turned on

each cycle when the oscillator sets the RS latch, and

turned off when the main current comparator, I

, resets

the RS latch. The peak inductor current at which I

resets

the RS latch is controlled by the voltage on the I

pin,

which is the output of the error amplifier EA. The differen-

tial amplifier, A1, produces a signal equal to the differential

voltage sensed across the output capacitor but re-refer-

ences it to the internal signal ground (SGND) reference.

The EAIN pin receives a portion of this voltage feedback

signal at the DIFFOUT pin which is compared to the

internal reference voltage by the EA. When the load current

increases, it causes a slight decrease in the EAIN pin

voltage

relative to the 0.8V reference, which in turn causes

the I

voltage to increase until the average inductor

current matches the new load current. After the top

MOSFET has turned off, the bottom MOSFET is turned on

for the rest of the period.

The top MOSFET drivers are biased from floating boot-

strap capacitor C

, which normally is recharged during

each off cycle through an external Schottky diode. When

decreases to a voltage close to V

OUT

, however, the loop

may enter dropout and attempt to turn on the top MOSFET

continuously. A dropout detector detects this condition

and forces the top MOSFET to turn off for about 400ns

every 10th cycle to recharge the bootstrap capacitor.

The main control loop is shut down by pulling Pin 1 (RUN/

SS) low. Releasing RUN/SS allows an internal 1.2µA

current source to charge soft-start capacitor C

. When

reaches 1.5V, the main control loop is enabled with the

voltage clamped at approximately 30% of its maximum

value. As C

continues to charge, I

is gradually re-

leased allowing normal operation to resume. When the

RUN/SS pin is low, all LTC1929 functions are shut down.

If V

OUT

has not reached 70% of its nominal value when C

has charged to 4.1V, an overcurrent latchoff can be

invoked as described in the Applications Information

section.

Low Current Operation

The LTC1929 operates in a continuous, PWM control

mode. The resulting operation at low output currents

optimizes transient response at the expense of substantial

negative inductor current during the latter part of the

period. The level of ripple current is determined by the

inductor value, input voltage, output voltage, and fre-

quency of operation.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the PLLIN pin. The

output of the phase detector at the PLLFLTR pin is also the

DC frequency control input of the oscillator that operates

over a 140kHz to 310kHz range corresponding to a DC

voltage input from 0V to 2.4V. When locked, the PLL aligns

the turn on of the top MOSFET to the rising edge of the

synchronizing signal. When PLLIN is left open, the PLLFLTR

pin goes low, forcing the oscillator to minimum frequency.

Input capacitance ESR requirements and efficiency losses

are substantially reduced because the peak current drawn

from the input capacitor is effectively divided by two and

power loss is proportional to the RMS current squared. A

two stage, single output voltage implementation can re-

duce input path power loss by 75% and radically reduce

the required RMS current rating of the input capacitor(s).

INTV

/EXTV

Power

Power for the top and bottom MOSFET drivers and most

of the IC circuitry is derived from INTV

. When the

EXTV

pin is left open, an internal 5V low dropout

regulator supplies INTV

power. If the EXTV

pin is

taken above 4.7V, the 5V regulator is turned off and an

internal switch is turned on connecting EXTV

to INTV

This allows the INTV

power to be derived from a high

efficiency external source such as the output of the regu-

lator itself or a secondary winding, as described in the

Applications Information section. An external Schottky

diode can be used to minimize the voltage drop from

EXTV

to INTV

in applications requiring greater than

the specified INTV

current.

Voltages up to 7V can be

applied to EXTV

for additional gate drive capability.

LTC1929/LTC1929-PG

OPERATIO

(Refer to Functional Diagram)

Differential Amplifier

This amplifier provides true differential output voltage

sensing. Sensing both V

OUT

and V

OUT

–

benefits regula-

tion in high current applications and/or applications hav-

ing electrical interconnection losses. The AMPMD pin

(LTC1929 only) allows selection of internal, precision feed-

back resistors for high common mode rejection differencing

applications, or direct access to the actual amplifier inputs

without these internal feedback resistors for other applica-

tions. The AMPMD pin is grounded to connect the internal

precision resistors in a unity-gain differencing application

(default for the LTC1929-PG), or tied to the INTV

pin to

bypass the internal resistors and make the amplifier inputs

directly available. The amplifier is a unity-gain stable, 2MHz

gain-bandwidth, >120dB open-loop gain design. The am-

plifier has an output slew rate of 5V/µs and is capable of

driving capacitive loads with an output RMS current typi-

cally up to 25mA. The amplifier is not capable of sinking

current and therefore must be resistively loaded to do so.

Power Good (PGOOD) Pin (LTC1929-PG Only)

The PGOOD pin is connected to an open drain of a

MOSFET. The MOSFET turns on and pulls the pin low when

the output is not within ±7.5% of its nominal output level

as determined by its resistive feedback divider. When the

output meets the ±7.5% requirement, the MOSFET is

turned off within 10µs and the pin is allowed to be pulled

up by an external source.

Short-Circuit Detection

The RUN/SS capacitor is used initially to limit the inrush

current from the input power source. Once the controllers

have been given time, as determined by the capacitor on

the RUN/SS pin, to charge up the output capacitors and

provide full load current, the RUN/SS capacitor is then

used as a short-circuit timeout circuit. If the output voltage

falls to less than 70% of its nominal output voltage the

RUN/SS capacitor begins discharging assuming that the

output is in a severe overcurrent and/or short-circuit

condition. If the condition lasts for a long enough period

as determined by the size of the RUN/SS capacitor, the

controller will be shut down until the RUN/SS pin voltage

is recycled. This built-in latchoff can be overidden by

providing a current >5µA at a compliance of 5V to the

RUN/SS pin. This current shortens the soft-start period

but also prevents net discharge of the RUN/SS capacitor

during a severe overcurrent and/or short-circuit condi-

tion. Foldback current limiting is activated when the output

voltage falls below 70% of its nominal level whether or not

the short-circuit latchoff circuit is enabled.

APPLICATIO S I FOR ATIO

WUU

The basic LTC1929 application circuit is shown in Figure␣ 1

on the first page. External component selection is driven

by the load requirement, and begins with the selection of

SENSE1, 2

. Once R

SENSE1, 2

are known, L1 and L2 can be

chosen. Next, the power MOSFETs and D1 and D2 are

selected. The operating frequency and the inductor are

chosen based mainly on the amount of ripple current.

Finally, C

is selected for its ability to handle the input

ripple current (that PolyPhase

operation minimizes) and

OUT

is chosen with low enough ESR to meet the output

ripple voltage and load step specifications (also minimized

with PolyPhase). Current mode architecture provides in-

herent current sharing between output stages. The circuit

shown in Figure␣ 1 can be configured for operation up to an

input voltage of 28V (limited by the external MOSFETs).

SENSE

Selection For Output Current

SENSE1, 2

are chosen based on the required output

current. The LTC1929 current comparator has a maxi-

mum threshold of 75mV/R

SENSE

and an input common

mode range of SGND to 1.1( INTV

). The current com-

parator threshold sets the peak inductor current, yielding

a maximum average output current I

MAX

equal to the peak

value less half the peak-to-peak ripple current, ∆I

Allowing a margin for variations in the LTC1929 and

external component values yields:

SENSE

= 2(50mV/I

MAX

)

PolyPhase is a trademark of Linear Technology Corporation.

LTC1929/LTC1929-PG

APPLICATIO S I FOR ATIO

WUU

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due to

internal compensation required to meet stability criterion

for buck regulators operating at greater than 50% duty

factor. A curve is provided to estimate this reduction in

peak output current level depending upon the operating

duty factor.

Operating Frequency

The LTC1929 uses a constant frequency, phase-lockable

architecture with the frequency determined by an internal

capacitor. This capacitor is charged by a fixed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to Phase-Locked Loop

and Frequency Synchronization in the Applications Infor-

mation section for additional information.

A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure␣ 2. As the operating frequency

is increased the gate charge losses will be higher, reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 310kHz.

MOSFET gate charge and transition losses. In addition to

this basic tradeoff, the effect of inductor value on ripple

current and low current operation must also be considered.

The PolyPhase approach reduces both input and output

ripple currents while optimizing individual output stages to

run at a lower fundamental frequency, enhancing efficiency.

The inductor value has a direct effect on ripple current. The

inductor ripple current ∆I

per individual section, N,

decreases with higher inductance or frequency and in-

creases with higher V

or V

OUT

∆I

OUT OUT

=−













where f is the individual output stage operating frequency.

In a 2-phase converter, the net ripple current seen by the

output capacitor is much smaller than the individual

inductor ripple currents due to the ripple cancellation. The

details on how to calculate the net output ripple current

can be found in Application Note 77.

Figure 3 shows the net ripple current seen by the output

capacitors for the 1- and 2-phase configurations. The

output ripple current is plotted for a fixed output voltage as

the duty factor is varied between 10% and 90% on the

x-axis. The output ripple current is normalized against the

inductor ripple current at zero duty factor. The graph can

be used in place of tedious calculations, simplifying the

design process.

Figure 2. Operating Frequency vs V

PLLFLTR

Figure 3. Normalized Output Ripple Current

vs Duty Factor [I

RMS

≈ 0.3 (∆I

O(P–P)

)]

OPERATING FREQUENCY (kHz)

120 170 220 270 320

PLLFLTR PIN VOLTAGE (V)

1929 F02

2.5

2.0

1.5

1.0

0.5

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

DUTY FACTOR (V

OUT

)

0.1 0.2 0.3 0.4

0.5 0.6 0.7 0.8 0.9

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1929 F03

2-PHASE

1-PHASE

∆I

O(P-P)

/fL

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