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AD9200ARSZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Parameter Symbol Min Typ Max Units Condition
DIGITAL INPUTS
High Input Voltage V
IH
2.4 V
Low Input Voltage V
IL
0.3 V
DIGITAL OUTPUTS
High-Z Leakage I
OZ
–10 +10 µA Output = GND to VDD
Data Valid Delay t
OD
25 ns C
L
= 20 pF
Data Enable Delay t
DEN
25 ns
Data High-Z Delay t
DHZ
13 ns
LOGIC OUTPUT (with DRVDD = 3 V)
High Level Output Voltage (I
OH
= 50 µA) V
OH
+2.95 V
High Level Output Voltage (I
OH
= 0.5 mA) V
OH
+2.80 V
Low Level Output Voltage (I
OL
= 1.6 mA) V
OL
+0.4 V
Low Level Output Voltage (I
OL
= 50 µA) V
OL
+0.05 V
LOGIC OUTPUT (with DRVDD = 5 V)
High Level Output Voltage (I
OH
= 50 µA) V
OH
+4.5 V
High Level Output Voltage (I
OH
= 0.5 mA) V
OH
+2.4 V
Low Level Output Voltage (I
OL
= 1.6 mA) V
OL
+0.4 V
Low Level Output Voltage (I
OL
= 50 µA) V
OL
+0.1 V
CLOCKING
Clock Pulsewidth High t
CH
22.5 ns
Clock Pulsewidth Low t
CL
22.5 ns
Pipeline Latency 3 Cycles
CLAMP
2
Clamp Error Voltage E
OC
±20 ±40 mV CLAMPIN = 0.5 V–2.7 V, R
IN
= 10 Ω
Clamp Pulsewidth t
CPW
2 µsC
IN
= 1 µF (Period = 63.5 µs)
NOTES
1
See Figures 1a and 1b.
2
Available only in AD9200ARS and AD9200KST.
Specifications subject to change without notice.
AD9200
REFTS
REFBS
MODE
AV
DD
10kV
10kV
0.4 3 V
DD
AD9200
REFTS
REFBF
MODE
REFTF
REFBS
4.2kV
Figure 1a. Figure 1b.
AD9200
–3–
REV. E
AD9200
–4–
REV. E
DRVDD
AVSS
DRVSS
DRVSS
AVDD
AVDD
AVSS
AVSS
AVDD
REFTF
REFTS
AVDD
AVSS
AVDD
AVSS
REFBS
REFBF
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
AVSS
AVDD
AVSS
AVDD
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter to Min Max Units
AVDD AVSS –0.3 +6.5 V
DRVDD DRVSS –0.3 +6.5 V
AVSS DRVSS –0.3 +0.3 V
AVDD DRVDD –6.5 +6.5 V
MODE AVSS –0.3 AVDD + 0.3 V
CLK AVSS –0.3 AVDD + 0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
AIN AVSS –0.3 AVDD + 0.3 V
VREF AVSS –0.3 AVDD + 0.3 V
REFSENSE AVSS –0.3 AVDD + 0.3 V
REFTF, REFTB AVSS –0.3 AVDD + 0.3 V
REFTS, REFBS AVSS –0.3 AVDD + 0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
10 sec +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Description Options*
AD9200JRS 0°C to +70°C 28-Lead SSOP RS-28
AD9200ARS –40°C to +85°C 28-Lead SSOP RS-28
AD9200JST 0°C to +70°C 48-Lead LQFP ST-48
AD9200KST 0°C to +70°C 48-Lead LQFP ST-48
AD9200JRSRL 0°C to +70°C 28-Lead SSOP (Reel) RS-28
AD9200ARSRL –40°C to +85°C 28-Lead SSOP (Reel) RS-28
AD9200JSTRL 0°C to +70°C 48-Lead LQFP (Reel) ST-48
AD9200KSTRL 0°C to +70°C 48-Lead LQFP (Reel) ST-48
AD9200 SSOP-EVAL Evaluation Board
AD9200 LQFP-EVAL Evaluation Board
*RS = Shrink Small Outline; ST = Thin Quad Flatpack.
Figure 2. Equivalent Circuits
a. D0–D9, OTR
b. Three-State, Standby, Clamp
c. CLK
d. AIN
e. Reference
f. CLAMPIN g. MODE
h. REFSENSE
i. VREF
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9200 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD9200
–5–
REV. E
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTIONS
SSOP LQFP
Pin No. Pin No. Name Description
1 44 AVSS Analog Ground
2 45 DRVDD Digital Driver Supply
3 1 D0 Bit 0, Least Significant Bit
4 2 D1 Bit 1
5 3 D2 Bit 2
6 4 D3 Bit 3
7 5 D4 Bit 4
8 8 D5 Bit 5
9 9 D6 Bit 6
10 10 D7 Bit 7
11 11 D8 Bit 8
12 12 D9 Bit 9, Most Significant Bit
13 16 OTR Out-of-Range Indicator
14 17 DRVSS Digital Ground
15 22 CLK Clock Input
16 23 THREE-STATE HI: High Impedance State. LO: Normal Operation
17 24 STBY HI: Power-Down Mode. LO: Normal Operation
18 26 REFSENSE Reference Select
19 27 CLAMP HI: Enable Clamp Mode. LO: No Clamp
20 28 CLAMPIN Clamp Reference Input
21 29 REFTS Top Reference
22 30 REFTF Top Reference Decoupling
23 32 MODE Mode Select
24 34 REFBF Bottom Reference Decoupling
25 35 REFBS Bottom Reference
26 38 VREF Internal Reference Output
27 39 AIN Analog Input
28 42 AVDD Analog Supply
28-Lead Shrink Small Outline (SSOP)
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9200
AVSS
REFBS
VREF
AIN
AVDD
DRVDD
D0
D1
REFTF
MODE
REFBF
D2
D3
D4
D5
D6
D7
CLAMP
CLAMPIN
REFTS
D8
D9
OTR
DRVSS
REFSENSE
CLK
THREE-STATE
STBY
48-Lead Plastic Thin Quad Flatpack (LQFP)
36
35
34
33
32
31
30
29
28
27
26
25
AVDD
VREF
NC
NC
NC
AVSS
NC
NC
AIN
NC
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
NC
REFBS
REFBF
NC
MODE
NC
REFTF
NC
NC
NC
NC
OTR
DRVSS
NC
D0
D1
D2
D3
D4
NC
NC
NC = NO CONNECT
D5
D6
D7
D8
REFTS
CLAMPIN
CLAMP
REFSENSE
NC
NC
CLK
THREE-STATE
NC
AD9200
STBY
D9
NC
DRVDD
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD9200ARSZ

Mfr. #:
Buy AD9200ARSZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10B 20MSPS 80mW CMOS
Lifecycle:
New from this manufacturer.
Delivery:
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