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AD9200ARSZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD9200
–6–
REV. E
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale”. The
point used as “zero” occurs 1/2 LSB before the first code transi-
tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
Typical Characterization Curves
CODE OFFSET
1.0
0.5
–1.0
0 1024128
DNL
256 384 512 640 768 896
0
–0.5
Figure 3. Typical DNL
CODE OFFSET
1.0
0.5
–1.0
0 1024128
INL
256 384 512 640 768 896
0
–0.5
Figure 4. Typical INL
Offset Error
The first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transi-
tion from that point.
Gain Error
The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 LSB below the nominal positive full
scale. Gain error is the deviation of the actual difference be-
tween first and last code transitions and the ideal difference
between the first and last code transitions.
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising edge.
INPUT FREQUENCY – Hz
60
55
20
1.00E+05 1.00E+081.00E+06 1.00E+07
50
45
25
40
35
30
SNR– dB
–0.5 AMPLITUDE
–6.0 AMPLITUDE
–20.0 AMPLITUDE
Figure 5. SNR vs. Input Frequency
60
55
20
1.00E+05 1.00E+081.00E+06
SINAD – dB
1.00E+07
50
45
25
40
35
30
–0.5 AMPLITUDE
–6.0 AMPLITUDE
–20.0 AMPLITUDE
INPUT FREQUENCY – Hz
Figure 6. SINAD vs. Input Frequency
(AVDD = +3 V, DRVDD = +3 V, F
S
= 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)
AD9200
–7–
REV. E
–30
–35
–80
1.00E+05 1.00E+081.00E+06 1.00E+07
–40
–45
–75
–60
–65
THD – dB
–70
–0.5 AMPLITUDE
–6.0 AMPLITUDE
–20.0 AMPLITUDE
INPUT FREQUENCY – Hz
–50
–55
CLOCK = 20MHz
Figure 7. THD vs. Input Frequency
CLOCK FREQUENCY – Hz
–70
–60
0
100E+03 100E+061E+06
THD – dB
10E+06
–50
–40
–10
–30
–20
F
IN
= 1MHz
Figure 8. THD vs. Clock Frequency
TEMPERATURE – °C
1.005
1.004
0.998
–40 100–20
V
REF
– V
0
1.003
1.002
0.999
1.001
1.000
20 40 60 80
Figure 9. Voltage Reference Error vs. Temperature
CLOCK FREQUENCY – MHz
80.5
80.0
77.0
0202
POWER CONSUMPTION – mW
4
79.5
79.0
77.5
78.5
78.0
6 8 10 12 14 16 18
CLOCK FREQUENCY – MHz
80.5
80.0
77.0
0202
POWER CONSUMPTION – mW
4
79.5
79.0
77.5
78.5
78.0
6 8 10 12 14 16 18
Figure 10. Power Consumption vs. Clock Frequency
(MODE = AVSS)
1M
900k
0
N–1 N
HITS
N+1
800k
700k
100k
400k
300k
200k
CODE
600k
500k
499856
54383
54160
Figure 11. Grounded Input Histogram
SINGLE TONE FREQUENCY DOMAIN
20
–60
–140
0E+0 10E+61E+6 2E+6 3E+6 4E+6 5E+6 6E+6 7E+6 8E+6 9E+6
0
–20
–100
–120
–40
–80
CLOCK = 20MHz
Figure 12. Single-Tone Frequency Domain
AD9200
–8–
REV. E
Table I. Mode Selection
Input Input MODE REFSENSE
Modes Connect Span Pin Pin REF REFTS REFBS Figure
TOP/BOTTOM AIN 1 V AVDD Short REFSENSE, REFTS and VREF Together AGND 18
AIN 2 V AVDD AGND Short REFTS and VREF Together AGND 19
CENTER SPAN AIN 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20
AIN 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2
Differential AIN Is Input 1 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29
REFTS and
REFBS Are
Shorted Together
for Input 2 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2
External Ref AIN 2 V max AVDD AVDD No Connect Span = REFTS 21, 22
– REFBS (2 V max)
AGND Short to Short to 23
VREFTF VREFBF
AD876 AIN 2 V Float or AVDD No Connect Short to Short to 30
AVSS VREFTF VREFBF
0
–9
1.0E+6 1.0E+910.0E+6
SIGNAL AMPLITUDE – dB
100.0E+6
–3
–6
FREQUENCY – Hz
–12
–15
–18
–21
–24
–27
Figure 13. Full Power Bandwidth
25
20
–25
0 3.01.0 2.0
15
10
–5
–10
–15
INPUT VOLTAGE – V
5
0
–20
2.50.5 1.5
I
B
– mA
REFBS = 0.5V
REFTS = 2.5V
CLOCK = 20MHz
Figure 14. Input Bias Current vs. Input Voltage
APPLYING THE AD9200
THEORY OF OPERATION
The AD9200 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9200 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD9200 requires a small fraction of the
1023 comparators used in a traditional flash type A/D. A
sample-and-hold function within each of the stages permits the
first stage to operate on a new input sample while the second,
third and fourth stages operate on the three preceding samples.
OPERATIONAL MODES
The AD9200 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD876 A/D.
To realize this flexibility, internal switches on the AD9200 are
used to reconfigure the circuit into different modes. These modes
are selected by appropriate pin strapping. There are three parts
of the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the appli-
cation will determine which mode is appropriate: the descrip-
tions in the following sections, as well as the Table I should
assist in picking the desired mode.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD9200ARSZ

Mfr. #:
Buy AD9200ARSZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10B 20MSPS 80mW CMOS
Lifecycle:
New from this manufacturer.
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