NCV8873
www.onsemi.com
8
THEORY OF OPERATION
Figure 10. Current Mode Control Schematic
Gm
CSA
Slope
Compensation
Q
D1
PWM
Comparator
Compensation
D2
Dn
NCV8873
Q
S
Gate
Driver
V
g
ISNS
GDRV
R
F1
VFB
VO
Oscillator
L
CO
RSNS
VREF
R
Current Mode Control
The NCV8873 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and error amplifier, which is commonly found
in voltage mode controllers. The second benefit comes from
inherent pulse−by−pulse current limiting by merely
clamping the peak switching current. Finally, since current
mode commands an output current rather than voltage, the
filter offers only a single pole to the feedback loop. This
allows for a simpler compensation.
The NCV8873 also includes a slope compensation
scheme in which a fixed ramp generated by the oscillator is
added to the current ramp. A proper slope rate is provided to
improve circuit stability without sacrificing the advantages
of current mode control.
Current Limit
The NCV8873 features a peak current−mode current limit
protection. When the current sense amplifier detects a
voltage above the peak current limit between ISNS and
GND after the current limit leading edge blanking time, the
peak current limit causes the power switch to turn off for the
remainder of the cycle. Set the current limit with a resistor
from ISNS to GND, with R = V
CL
/ I
limit
.
If the voltage across the current sense resistor exceeds the
over current threshold voltage the part enters over current
hiccup mode. The part will remain off for the hiccup time
and then go through the soft−start procedure.
EN/SYNC
This pin has three modes. When a dc logic high
(CMOS/TTL compatible) voltage is applied to this pin the
NCV8873 operates at the programmed frequency. When a
dc logic low voltage is applied to this pin the NCV8873
enters a low quiescent current sleep mode. When a square
wave of at least %f
sync,min
of the free running switching
frequency is applied to this pin, the switcher operates at the
same frequency as the square wave. If the signal is slower
than this, it will be interpreted as enabling and disabling the
part. The falling edge of the square wave corresponds to the
start of the switching cycle. If an Enable command is
received during normal operation, the minimum duration of
the Enable low−state must be greater than 7 clock cycles.
If the VIN pin voltage falls below V
UVLO
when
EN/SYNC pin is at logic−high, the IC may not power up
when VIN returns back above the UVLO. To resume a
normal operating state, the EN/SYNC pin must be cycled
with a single logic−low to logic−high transition.
UVLO
Input Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
and will shut down when VIN drops below the UVLO
threshold or the part is disabled.
To avoid any lock state under UVLO conditions, the
EN/SYNC pin should be in logic−low state. For further
details, please refer to EN/SYNC paragraph.
Internal Soft−Start
To insure moderate inrush current and reduce output
overshoot, the NCV8873 features a soft start which charges a
capacitor with a fixed current to ramp up the reference voltage.
This fixed current is based on the switching frequency, so that
