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MC100LVEL11DG

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 13
1 Publication Order Number:
MC100LVEL11/D
MC100LVEL11
3.3V ECL 1:2
Differential Fanout Buffer
Description
The MC100LVEL11 is a differential 1:2 fanout buffer. The device is
functionally similar to the E111 device but with higher performance
capabilities. Having within-device skews and output transition times
significantly improved over the E111, the LVEL11 is ideally suited for
those applications which require the ultimate in AC performance.
The differential inputs of the LVEL11 employ clamping circuitry to
maintain stability under open input conditions. If the inputs are left
open (pulled to V
EE
) the Q outputs will go LOW.
Features
• 330 ps Propagation Delay
• 5 ps Skew Between Outputs
• High Bandwidth Output Transitions
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −3.8 V
• Internal Input Pulldown Resistors on D,
Pullup and Pulldown Resistors on D
• Q Output will Default LOW with Inputs Open or at V
EE
• These Devices are Pb−Free and are RoHS Compliant
1
2
3
4
5
6
7
8
D
V
EE
V
CC
Figure 1. Logic Diagram and Pinout Assignment
Q
0
Q
0
DQ
1
Q
1
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
KV11
ALYWG
G
SOIC−8
D SUFFIX
CASE 751
1
8
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
www.onsemi.com
KVL11
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
(Note: Microdot may be in either location)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
1
3ZMG
G
1
MC100LVEL11
www.onsemi.com
2
Table 1. PIN DESCRIPTION
Pin Function
Q0, Q0; Q1, Q1 ECL Data Outputs
D, D ECL Data Inputs
V
CC
Positive Supply
V
EE
Negative Supply
EP (DFN8 only) Thermal exposed pad must be connected to a suffi-
cient thermal conduit. Electrically connect to the most negative
supply (GND) or leave unconnected, floating open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
75 kW
ESD Protection Human Body Model
Machine Model
Charge Device Model
> 4 KV
> 400 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 63
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Units
V
CC
PECL Mode Power Supply V
EE
= 0 V 8 to 0 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −8 to 0 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
6 to 0
−6 to 0
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
T
A
Operating Temperature Range −40 to +95 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lpfm
500 lpfm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 ± 5% °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lpfm
500 lpfm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder Pb−Free <2 to 3 sec @ 260°C 265 °C
q
JC
Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
MC100LVEL11
www.onsemi.com
3
Table 4. LVPECL DC CHARACTERISTICS V
CC
= 3.3 V; V
EE
= 0.0 V (Note 3)
−40°C 25°C 95°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 24 28 24 28 25 30 mA
V
OH
Output HIGH Voltage (Note 4) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV
V
OL
Output LOW Voltage (Note 4) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV
V
IH
Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV
V
IL
Input LOW Voltage (Single−Ended) 1490 1825 1490 1825 1490 1825 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
V
pp
< 500 mV
V
pp
y 500 mV
1.2
1.4
3.1
3.1
1.1
1.3
3.1
3.1
1.1
1.3
3.1
3.1
V
V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current D
D
0.5
−600
0.5
−600
0.5
−600
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
4. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
5. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1.0 V.
Table 5. LVNECL DC CHARACTERISTICS V
CC
= 0.0 V; V
EE
= −3.3 V (Note 6)
−40°C 25°C 95°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 24 28 24 28 25 30 mA
V
OH
Output HIGH Voltage (Note 7) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV
V
OL
Output LOW Voltage (Note 7) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV
V
IH
Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV
V
IL
Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
V
pp
< 500 mV
V
pp
y 500 mV
−2.1
−1.9
−0.2
−0.2
−2.2
−2.0
−0.2
−0.2
−2.2
−2.0
−0.2
−0.2
V
V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current D
D
0.5
−600
0.5
−600
0.5
−600
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
7. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
8. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1.0 V.
P1-P3P4-P6P7-P8

MC100LVEL11DG

Mfr. #:
Buy MC100LVEL11DG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V ECL 1:2 Diff Fanout Buffer
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