MC100LVEL11DG

MC100LVEL11
www.onsemi.com
4
Table 6. AC CHARACTERISTICS V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
= −3.3 V (Note 9)
−40°C 25°C 95°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
max
Maximum Toggle Frequency 1.0 GHz
t
PLH
t
PHL
Propagation Delay to Output 235 385 255 330 405 285 435 ps
t
SKEW
Within-Device Skew (Note 10)
Device−to−Device (Note 11)
Duty Cycle Skew (Note 12)
5
10
20
150
20
5
10
20
150
20
5
10
20
150
20
ps
t
JITTER
Random Clock Jitter (RMS) 0.6 ps
V
PP
Input Swing (Note 13) 200 1000 200 1000 200 1000 mV
t
r
t
f
Output Rise/Fall Times Q
(20% − 80%)
120 320 120 220 320 120 320 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
9. V
EE
can vary ±0.3 V.
10.Within-device skew defined as identical transitions on similar paths through a device.
11. Device−to−device skew for identical transitions at identical V
CC
levels.
12.Duty cycle skew is the difference between a t
PLH
and t
PHL
propagation delay through a device.
13.V
PP
(min) is the minimum input swing for which AC parameters guaranteed. The device will function properly with input swings below 200 mV,
however, AC delays may move outside of the specified range. The device has a DC gain of 40.
Figure 2. Output Swing versus Frequency
0
200
400
600
800
0 200 400 600 800 1000 1200 1400 1600 1800 2000
f (MHz)
V
OUT(PP)
(mV)
MC100LVEL11
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5
ORDERING INFORMATION
Device Package Shipping
MC100LVEL11DG SOIC−8
(Pb−Free)
98 Units / Rail
MC100LVEL11DR2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100LVEL11DTG TSSOP−8
(Pb−Free)
100 Units / Rail
MC100LVEL11DTR2G TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100LVEL11MNR4G DFN8
(Pb−Free)
1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
MC100LVEL11
www.onsemi.com
6
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z
S
X
S
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒ
mm
inches
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*

MC100LVEL11DG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V ECL 1:2 Diff Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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