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553SCMGI

P1-P3P4-P6P7-P9P10-P12
LOW SKEW 1 TO 4 CLOCK BUFFER 4 REVISION A 03/18/15
553S DATASHEET
DC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD=1.8V ±5% , Ambient temperature -40° to +105°C, unless stated otherwise
Notes: 1. Nominal switching threshold is VDD/2
VDD=2.5 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
VDD=3.3 V ±5% , Ambient temperature -40° to +105°C, unless stated otherwise
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 1.71 1.89 V
Input High Voltage, ICLK V
IH
Note 1 0.7xVDD VDD V
Input Low Voltage, ICLK V
IL
Note 1 0.3xVDD V
Input High Voltage, OE V
IH
0.7xVDD VDD V
Input Low Voltage, OE V
IL
0.3xVDD V
Output High Voltage V
OH
I
OH
= -10mA 1.3 V
Output Low Voltage V
OL
I
OL
= 10mA 0.35 V
Operating Supply Current IDD No load, 135MHz 15 mA
Nominal Output Impedance Z
O
17
Input Capacitance C
IN
ICLK, OE pin 5 pF
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 2.375 2.625 V
Input High Voltage, ICLK V
IH
Note 1 0.7xVDD VDD V
Input Low Voltage, ICLK V
IL
Note 1 0.3xVDD V
Input High Voltage, OE V
IH
0.7xVDD VDD V
Input Low Voltage, OE V
IL
0.3xVDD V
Output High Voltage V
OH
I
OH
= -16 mA 1.8 V
Output Low Voltage V
OL
I
OL
= 16 mA 0.5 V
Operating Supply Current IDD No load, 135 MHz 18 mA
Nominal Output Impedance Z
O
17
Input Capacitance C
IN
ICLK, OE pin 5 pF
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.15 3.45 V
Input High Voltage, ICLK V
IH
Note 1 0.7xVDD VDD V
Input Low Voltage, ICLK V
IL
Note 1 0.3xVDD V
Input High Voltage, OE V
IH
0.7xVDD VDD V
Input Low Voltage, OE V
IL
0.3xVDD V
Output High Voltage V
OH
I
OH
= -25 mA 2.2 V
Output Low Voltage V
OL
I
OL
= 25 mA 0.7 V
Operating Supply Current IDD No load, 135 MHz 22 mA
Nominal Output Impedance Z
O
17
Input Capacitance C
IN
ICLK, OE pin 5 pF
REVISION A 03/18/15 5 LOW SKEW 1 TO 4 CLOCK BUFFER
553S DATASHEET
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
VDD = 2.5 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
VDD = 3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency 0 200 MHz
Output Rise Time t
OR
0.36 to 1.44 V, C
L
=5 pF 0.6 1.0 ns
Output Fall Time t
OF
1.44 to 0.36 V, C
L
=5 pF 0.6 1.0 ns
Propagation Delay Note 1 2.5 3 3.5 ns
Buffer Additive Phase Jitter, RMS 125MHz, Integration Range: 12kHz-20MHz 0.05 ps
Output to Output Skew Note 2 Rising edges at VDD/2 50 65 ps
Device to Device Skew Rising edges at VDD/2 200 ps
Start-up Time t
START-UP
Part start-up time for valid outputs after
VDD ramp-up
2ms
Output Enable Time t
EN
C
L
< 5 pF 3 cycles
Output Disable Time t
DIS
C
L
< 5 pF 3 cycles
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency 0 200 MHz
Output Rise Time t
OR
0.5 to 2.0 V, C
L
=5 pF 0.6 1.0 ns
Output Fall Time t
OF
2.0 to 0.5 V, C
L
=5 pF 0.6 1.0 ns
Propagation Delay Note 1 3 3.5 4 ns
Buffer Additive Phase Jitter, RMS 125MHz, Integration Range: 12kHz-20MHz 0.05 ps
Output to Output Skew Note 2 Rising edges at VDD/2 40 65 ps
Device to Device Skew Rising edges at VDD/2 200 ps
Start-up Time t
START-UP
Part start-up time for valid outputs after
VDD ramp-up
2ms
Output Enable Time t
EN
C
L
< 5 pF 3 cycles
Output Disable Time t
DIS
C
L
< 5 pF 3 cycles
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency 0 200 MHz
Output Rise Time t
OR
0.66 to 2.64 V, C
L
=5 pF 0.6 1.0 ns
Output Fall Time t
OF
2.64 to 0.66 V, C
L
=5 pF 0.6 1.0 ns
Propagation Delay Note 1 2.5 3 3.5 ns
Buffer Additive Phase Jitter, RMS 125MHz, Integration Range: 12kHz-20MHz 0.05 ps
Output to Output Skew Note 2 Rising edges at VDD/2 25 65 ps
Device to Device Skew Rising edges at VDD/2 200 ps
Start-up Time t
START-UP
Part start-up time for valid outputs after
VDD ramp-up
2ms
Output Enable Time t
EN
C
L
< 5 pF 3 cycles
Output Disable Time t
DIS
C
L
< 5 pF 3 cycles
LOW SKEW 1 TO 4 CLOCK BUFFER 6 REVISION A 03/18/15
553S DATASHEET
Phase Noise Plots
The phase noise plots above show the low Additive Jitter of the 553S high-performance buffer. With an integration range of
12kHz to 20MHz, the reference input has about 66fs of RMS phase jitter while the output of 553S has about 76fs of RMS phase
jitter. This results in a low Additive Phase Jitter of only 37fs.
Test Load and Circuit
Figure 1. 553S Reference Phase Noise 66fs
(12kHz to 20MHz)
Figure 2. 553S Output Phase Noise 76fs
(12kHz to 20MHz)
Rs=33ohm
5
i
n
c
h
e
s
CL = 5pF
50ohms
P1-P3P4-P6P7-P9P10-P12

553SCMGI

Mfr. #:
Buy 553SCMGI
Manufacturer:
IDT
Description:
Clock Buffer Low Skew 1 to 4 50fs 200MHz 3.465V
Lifecycle:
New from this manufacturer.
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