CP2112
10 Rev. 1.2
Figure 2. QFN-24 Pinout Diagram (Top View)
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
18
17
16
15
14
13
GND (optional)
CP2112-GM
Top View
NC
GPIO.3
GPIO.2
GPIO.1_RXT
GPIO.0_TXT
SCL
SDA
GND
D+
N/C
SUSPEND
GPIO.7_CLK
NC
GPIO.6
GPIO.5
GPIO.4
VPP
SUSPEND
VDD
VIO
D-
RST
VBUS
REGIN
CP2112
Rev. 1.2 11
4. QFN-24 Package Specifications
Figure 3. QFN-24 Package Drawing
Table 8. QFN-24 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A 0.70 0.75 0.80 L 0.30 0.40 0.50
A1 0.00 0.02 0.05 L1 0.00 0.15
b 0.18 0.25 0.30 aaa 0.15
D 4.00 BSC. bbb 0.10
D2 2.55 2.70 2.80 ddd 0.05
e 0.50 BSC. eee 0.08
E 4.00 BSC. Z 0.24
E2 2.55 2.70 2.80 Y 0.18
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
CP2112
12 Rev. 1.2
Figure 4. QFN-24 Recommended PCB Land Pattern
Table 9. QFN-24 PCB Land Pattern Dimensions
Dimension Min Max Dimension Min Max
C1 3.90 4.00 X2 2.70 2.80
C2 3.90 4.00 Y1 0.65 0.75
E 0.50 BSC Y2 2.70 2.80
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder-mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center
pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small
body components.

CP2112-F02-GMR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
USB Interface IC HID USB to SMBUS Bridge QFN24
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet