AVR Studio Emulator Options
5-2 AVR
®
ATICE30 User Guide
5.5 Advanced
(ATmega163,
ATmega161,
ATmega83 and
ATmega32)
In order to emulate the enhanced instruction set featured by the enhanced AVR archi-
tecture (ATmega163/161/83/32), the option Enable Enhanced Instruction Set must be
checked.
Note: When emulating the enhanced instruction set, emulation will no longer be in real
time. See Section 6 Emulator Limitations for a detailed description.
AVR
®
ATICE30 User Guide 6-1
Section 6
Emulator Limitations
6.1 Enhanced AVR
Architecture
ATmega163/83, ATmega161 and ATmega32 use an enhanced AVR architecture sup-
porting new features and instructions. The following features have been added in the
new architecture.
A powerful 2-cycle hardware multiplier supporting both signed/unsigned multiplication
and fractional format.
The XRAM interface has been given a longer hold time, thereby meeting the timing
requirements of earlier unsupported external memory devices.
Extended LPM/ELPM instructions that now support both post-increment and the
possibility to select destination register.
Self-programming capabilities. The program memory can be reprogrammed by the
MCU itself.
Move Word (MOVW) instruction enabling one-cycle 16-bits register copy.
The only device supporting the new XRAM interface is ATmega161. The XRAM access
will internally take one clock cycle longer in the emulator compared to the actual device.
For the accessed XRAM, the timing will be identical to that of an actual ATmega161
device.
The AVR ICE30 is built around the standard AVR core. Therefore, it does not directly
support the Enhanced Instruction Set of the AVR enhanced architecture. As a
workaround, these instructions are implemented in software in the emulator
microcontroller.
To enable the Enhanced Instruction Set emulation, select the option Enable Enhanced
Instruction Set in the Options > Emulator Options dialog in AVR Studio.
If enabled, the emulator will stop when reaching an Enhanced Instruction Set instruc-
tion, and the emulator MCU will perform the actions needed to emulate the instruction.
This will typically be calculations and writing to the involved registers. This will take sub-
stantially longer time compared to the time used by the instruction in an actual AVR
device. Table 6-1 shows how long the emulation will be stopped when emulating the dif-
ferent instructions. These emulation times will be independent of the target frequency.
If the BOOTRST fuse is programmed (0), there will also be an emulation break when the
emulator reaches address 0x0000. This will happen both after a reset, after a jump to
address 0x0000 and after a wraparound from the last instruction in the program
memory.
Emulator Limitations
6-2 AVR
®
ATICE30 User Guide
Notes: 1. Only if the Enable Enhanced Instruction Set option is selected.
2. Only if BOOTRST fuse is programmed. Will also occur immediately after a reset.
3. If SPM is executed from the application section, or the lock bits are programmed and
therefore SPM is ignored, the emulation break time will be approximately 1.1 ms.
When emulating these instructions, the emulator IO clock is stopped. This means that
any ongoing UART, SPI or I2C transmission/reception or PWM will be frozen, and there-
fore produce erroneous signals. To avoid this, the program should wait for any
transmission/reception or PWM to finish before the enhanced instruction is executed.
Some applications have time-critical tasks where these emulation breaks are not
acceptable. If this is so, the program should not use any of the Enhanced Instruction Set
instructions shown in Table 6-2. Nor should the BOOTRST fuse be programmed if the
program during execution jumps to addr 0x0000.
In the IAR C-compiler an option can be set whether the code should be compiled for the
standard or the enhanced AVR architecture. This option can be found in Project >
Options > General > Target > Processor Configuration > Enhanced Core.
Table 6-1. Enhanced Instruction Emulation Break Time
Instruction Emulation Break Time [ms]
MOVW 3,4
LPM
(1)
3,6
LPM Rd,Z 3,6
LPM Rd,Z+ 3,8
ELPM
(2)
4,6
ELPM Rd,Z 4,6
ELPM Rd,Z+ 4,9
MUL 5,8
MULS 5,8
MULSU 5,8
FMUL 5,8
FMULS 5,8
FMULSU 5,8
SPM (SPMCR=0x01)
(3)
5,7
SPM (SPMCR=0x03)
(3)
11,5
SPM (SPMCR=0x05)
(3)
26,8
SPM (SPMCR=0x09)
(3)
2,4
JMP to Addr 0x0000 0,8

ATICE30

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EMULATOR IN CIRCUIT MEGAAVR
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