MAX2369
Complete Dual-Band
Quadrature Transmitter
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BIT NAME FUNCTION
IF_PLL_SHDN 1 0 shuts down the IF PLL. This mode is used with an external IF VCO and IF PLL.
UNUSED 1 Set to 0 for normal operation.
UNUSED 0 Set to 0 for normal operation.
ICP 00
A 2-bit register sets the IF charge-pump current as follows:
00 = 200µA
01 = 260µA
10 = 400µA
11 = 530µA
VCO_BYPASS 0 1 bypasses IF VCO and enables a buffered input for external VCO use.
BUF_DIV 0 1 selects ÷2 on IFLO port; 0 bypasses the divider.
IQ_LEVEL 1 1 selects 200mV
RMS
input mode; 0 selects 100mV
RMS
input mode.
UNUSED 00 Not used. Leave in the power-up/initialized state.
15
14
13
9, 8
10
11
12
7, 6
IF_PD_POL 1 5
IF phase-detector polarity; 1 selects positive polarity (increasing tuning voltage
on the VCO produces increasing frequency); 0 selects negative polarity
(increasing tuning voltage on the VCO produces decreasing frequency).
UNUSED 111 4, 3 ,2 Not used. Leave in the power-up/initialized state.
LD_MODE 1 0
Determines output mode for LOCK detector pin as follows:
0 = test mode, LD_MODE cannot be 0 for normal operation
1 = IF PLL lock detector
POWER-UP
STATE
BIT
LOCATION
(0 = LSB)
Table 4. Configuration Register (CONFIG)
Electromagnetic
Compliance Considerations
Two major concepts should be employed to produce a
noise-free and EMC-compliant transmitter: minimize cir-
cular current-loop area to reduce H-field radiation and
minimize voltage drops to reduce E-field radiation. To
minimize the circular current-loop area, bypass as
close to the part as possible and use the distributed
capacitance of a ground plane. To minimize voltage
drops, make V
CC
traces short and wide, and make RF
traces short.
The “don't care” bits in the registers should be zero in
order to minimize electromagnetic radiation due to
unnecessary bit banging. RC filtering can also be used
to slow the clock edges on the 3-wire interface, reduc-
ing high-frequency spectral content. RC filtering also
provides for transient protection against IEC802 testing
by shunting high frequencies to ground, while the
series resistance attenuates the transients for error-free
operation. The same applies to the override pins
(SHDN, TXGATE).
When floating the override pins, bypass to ground with
the capacitors as close to the part as possible.
High-frequency bypass capacitors are required close
to the pins with a dedicated via to ground. The 48-pin
QFN-EP package provides minimal inductance ground
by using an exposed paddle under the part. Provide at
least five low-inductance vias under the paddle to
ground to minimize ground inductance. Use a solid
ground plane wherever possible. Any cutout in the
ground plane may act as slot radiator and reduce its
shield effectiveness.
Keep the RF LO traces as short as possible to reduce
LO radiation and susceptibility to interference.
UNUSED 1 1 Set to 0 for normal operation.
