MAX2369
Complete Dual-Band
Quadrature Transmitter
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Detailed Description
The MAX2369 complete quadrature transmitter accepts
differential I/Q baseband inputs with external common-
mode bias. A modulator upconverts this to IF frequency
in the 120MHz to 235MHz range. A gain control voltage
pin (VGC) controls the gain of both the IF and RF VGAs
simultaneously to achieve best noise and linearity per-
formance. The IF signal is brought off-chip for filtering,
then fed to a single sideband upconverter followed by
the RF VGA and PA driver. The RF upconverter requires
an external VCO for operation. The IF PLL and operat-
ing mode can be programmed by an SPI/QSPI/
MICROWIRE-compatible 3-wire interface.
The following sections describe each block in the
MAX2369 Functional Diagram.
I/Q Modulator
Differential in-phase (I) and quadrature-phase (Q) input
pins are designed to be DC-coupled and biased with the
baseband output from a digital-to-analog converter
(DAC). I and Q inputs need a DC bias of V
CC
/2 and a
current-drive capability of 6µA. Common-mode voltage
will work within a 1.35V to (V
CC
- 1.25V) range. Typically,
I and Q will be driven differentially with a 200mV
RMS
baseband signal. Optionally, I and Q may be pro-
grammed for 100mV
RMS
operation with the IQ_LEVEL bit
in the configuration register. The IF VCO output is fed
into a divide-by-two/quadrature generator block to derive
quadrature components to drive the IQ modulator. The
output of the modulator is fed into the VGA.
IF VCO
The VCO oscillates at twice the desired IF frequency.
Oscillation frequency is determined by external tank
components (see Applications Information). Typical
phase-noise performance for the tank is shown in
Typical Operating Characteristics.
IFLO Output Buffer
IFLO provides a buffered LO output when BUF_EN is 1.
The IFLO output frequency is equal to the VCO fre-
quency when BUF_DIV is 0, and half the VCO frequen-
cy when BUF_DIV is 1. The output power is -6dBm. This
output is used in test mode.
IF PLL
The IF PLL uses a charge-pump output to drive a loop
filter. The loop filter will typically be a passive second-
order lead lag filter. Outside the filter’s bandwidth,
phase noise will be determined by the tank compo-
nents. The two components that contribute most signifi-
cantly to phase noise are the inductor and varactor.
Use high-Q inductors and varactors to maximize equiv-
alent parallel resistance. The ICP_MAX bit in the OPC-
TRL register can be set to 1 to increase the charge
pump current.
IF VGA
The IF VGA allows varying an IF output level that is con-
trolled by the VGC voltage. The voltage range on VGC
of +0.5V to +2.6V provides a gain-control range of
85dB. The IF output ports from the VGA are optimized
for IF frequency from 120MHz to 235MHz. IFOUT ports
support direct VCO FM modulation. The differential IF
output port has an output impedance of 600Ω when
pulled up to V
CC
through a choke.
Single Sideband Mixer
The RF transmit mixer uses a single sideband architec-
ture to eliminate an off-chip RF filter. The mixer is fol-
lowed by the RF VGA. The RF VGA is controlled by the
same VGC pin as the IF VGA to provide optimum lineari-
ty and noise performance. The total power control range
is >100dB.
PA Driver
The MAX2369 includes two power-amplifier (PA) drivers.
Each is optimized for the desired operating frequency.
RFL is optimized for cellular-band operation. RFH is opti-
mized for PCS operation. The PA drivers have open-col-
lector outputs and require pullup inductors. The pullup
inductors can act as the shunt element in a shunt series
match.
Programmable Registers
The MAX2369 includes five programmable registers
consisting of two divide registers, a configuration regis-
ter, an operational control register, and a test register.
Each register consists of 24 bits. The 4 least significant
bits (LSBs) are the register’s address. The 20 most sig-
nificant bits (MSBs) are used for register data. All regis-
ters contain some “don't care” bits. These can be either
a zero or a 1 and do not affect operation (Figure 1).
Data is shifted in MSB first, followed by the 4-bit
address. When CS is low, the clock is active and data
is shifted with the rising edge of the clock. When CS
transitions to high, the shift register is latched into the
register selected by the contents of the address bits.
Power-up defaults for the five registers are shown in
Table 1. The registers should be initialized according to
Table 2. The dividers and control registers are pro-
grammed from the SPI/QSPI/MICROWIRE-compatible
serial port.
