ISL95808
7
FN8689.2
May 25, 2016
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MOSFET gate-to-source voltage has dropped below a threshold of
1V, the LGATE is allowed to rise.
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode. Simply
adding an external capacitor across the Boot and Phase pins
completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage rating
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be derived from Equation 1
:
Where Q
GATE
is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The V
BOOT
term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate charge,
Q
GATE
, of 25nC at 5V and also assume the droop in the drive
voltage over a PWM cycle is 200mV. One will find that a
bootstrap capacitance of at least 0.125µF is required. The next
larger standard value capacitance is 0.15µF. A good quality
ceramic capacitor is recommended.
Power Dissipation
Package power dissipation is mainly a function of the switching
frequency and total gate charge of the selected MOSFETs.
Calculating the power dissipation in the driver for a desired
application is critical to ensuring safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. When designing the driver into an
application, it is recommended that the following calculation be
performed to ensure safe operation at the desired frequency for
the selected MOSFETs. The power dissipated by the driver is
approximated, as shown in Equation 2
:
Where f
SW
is the switching frequency of the PWM signal. V
U
and
V
L
represent the upper and lower gate rail voltage. Q
U
and Q
L
is
the upper and lower gate charge determined by MOSFET
selection and any external capacitance added to the gate pins.
The lV
CC
V
CC
product is the quiescent power of the driver and is
typically negligible.
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices (both
upper and lower FETs) could cause increased PHASE ringing,
which may lead to voltages that exceed the absolute maximum
rating of the devices. When PHASE rings below ground, the
negative voltage could add charge to the bootstrap capacitor
through the internal bootstrap diode. Under worst-case
conditions, the added charge could overstress the Boot and/or
Phase pins. To prevent this from happening, the user should
perform a careful layout inspection to reduce trace inductances,
and select low lead inductance MOSFETs and drivers. D
2
PAK and
DPAK packaged MOSFETs have high parasitic lead inductances.
If higher inductance MOSFETs must be used, a Schottky diode is
recommended across the lower MOSFET to clamp negative
phase ring.
A good layout would help reduce the ringing on the phase and
gate nodes significantly:
• Avoid using vias for decoupling components where possible,
especially in the Boot-to-Phase path. Little or no use of vias for
VCC and GND is also recommended. Decoupling loops should
be short.
• All power traces (UGATE, PHASE, LGATE, GND and VCC) should
be short and wide, and avoid using vias. If vias must be used,
two or more vias per layer transition is recommended.
• Keep the SOURCE of the upper FET as close as thermally
possible to the DRAIN of the lower FET.
• Keep the connection in between the SOURCE of lower FET and
power ground wide and short.
• Input capacitors should be placed as close to the DRAIN of the
upper FET and the SOURCE of the lower FET as thermally
possible.
C
BOOT
Q
GATE
V
BOOT
------------------------
(EQ. 1)
FIGURE 5. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
V
BOOT_CAP
(V)
C
BOOT_CAP
(µF)
2.0
1.6
1.4
1.0
0.8
0.6
0.4
0.2
0.0
0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
Q
GATE
= 100nC
1.2
1.8
50nC
20nC
Pf
SW
1.5V
U
Q
U
V
L
Q
L
+I
VCC
V
CC
+=
(EQ. 2)
FIGURE 6. POWER DISSIPATION vs FREQUENCY
FREQUENCY (kHz)
0
100
200
300
400
500
600
700
800
900
1000
0 200 400 600 800 1000 1200 1400 1600 1800 2000
POWER (mW)
Q
U
= 50nC
Q
L
= 50nC
Q
U
= 50nC
Q
L
= 100nC
Q
U
=100nC
Q
L
= 200nC
Q
U
= 20nC
Q
L
=50nC
