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HCPL-J314

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13
Selecting the Gate Resistor (Rg)
Step 1: Calculate R
g
minimum from the I
OL
peak speci-
cation. The IGBT and Rg in Figure 19 can be analyzed as
a simple RC circuit with a voltage supplied by the HCPL-
J314.
V
CC
– V
OL
Rg ≥ ————
I
OLPEAK
24 V – 5 V
= ————
0.6A
= 32 Ω
The V
OL
value of 5 V in the previous equation is the V
OL
at the peak current of 0.6A. (See Figure 6).
Step 2: Check the HCPL-J314 power dissipation and in-
crease Rg if necessary. The HCPL-J314 total power dissi-
pation (P
T
) is equal to the sum of the emitter power (P
E
)
and the output power (P
O
).
P
T
= P
E
+ P
O
P
E
= I
F
6 V
F
6 Duty Cycle
P
O
= P
O(BIAS)
+ P
O(SWITCHING)
= I
CC
6 V
CC
+ E
SW
(Rg,Qg) 6 f
= (I
CCBIAS
+ K
ICC
6 Qg 6 f) 6 V
CC
+ E
SW
(Rg,Qg) 6 f
where K
ICC
6 Qg 6 f is the increase in I
CC
due to switch-
ing and K
ICC
is a constant of 0.001 mA/(nC*kHz). For the
circuit in Figure 19 with I
F
(worst case) = 10 mA, Rg = 32
Ω, Max Duty Cycle = 80%, Qg = 100 nC, f = 20 kHz and
T
AMAX
= 85°C:
P
E
= 10 mA 6 1.8 V 6 0.8 = 14 mW
P
O
= (3 mA + (0.001 mA/(nC 6 kHz)) 6 20 kHz 6 100 nC) 6
24 V + 0.4 µJ 6 20 kHz = 80 mW
< 260 mW (P
O(MAX)
@ 85°C)
The value of 3 mA for I
CC
in the previous equation is the
max. I
CC
over entire operating temperature range.
Since P
O
for this case is less than P
O(MAX)
, Rg = 32 Ω is all
right for the power dissipation.
Figure 20. Energy dissipated in the HCPL-J314 and for
each IGBT switching cycle.
LED Drive Circuit Considerations for Ultra High CMR Perfor-
mance
Without a detector shield, the dominant cause of op-
tocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 21. The HCPL-J314
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the ca-
pacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 22. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED in
the proper state (on or o) during common mode tran-
sients. For example, the recommended application circuit
(Figure 19), can achieve 10 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in the proper state are
discussed in the next two sections.
Esw – ENERGY PER SWITCHING CYCLE – µJ
0
0
Rg – GATE RESISTANCE – Ω
100
1.5
20
4.0
40
1.0
60 80
3.5
Qg = 50 nC
Qg = 100 nC
Qg = 200 nC
Qg = 400 nC
3.0
2.0
0.5
2.5
14
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING ÐdV
CM
/dt.
+5 V
+
-
V
CC
= 18 V
***
***
0.1
µF
+
-
-
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Figure 21. Optocoupler input to output capacitance
model for unshielded optocouplers.
Figure 22. Optocoupler input to output capacitance
model for shielded optocouplers.
Figure 23. Equivalent circuit for Figure 17 during common mode transient.
Figure 24. Not recommended open collector drive circuit. Figure 25. Recommended LED drive circuit for ultra-high CMR
IPM dead time and propagation delay specications.
HCPL-J314 fig 22
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
CMR with the LED On (CMR
H
)
A high CMR LED drive circuit must keep the LED on
during common mode transients. This is achieved by
overdriving the LED current beyond the input threshold
so that it is not pulled below the threshold during a
transient. A minimum LED current of 8 mA provides
adequate margin over the maximum IFigure 26. Minimum
LED Skew for Zero Dead Time.Figure 27. Waveforms for
Dead Time. of 5 mA to achieve 10 kV/µs CMR.
CMR with the LED O (CMR
L
)
A high CMR LED drive circuit must keep the LED o (V
F
≤ V
F(OFF)
) during common mode transients. For example,
during a -dV
CM
/dt transient in Figure 23, the current
owing through C
LEDP
also ows through the RSAT and
VSAT of the logic gate. As long as the low state voltage
developed across the logic gate is less than V
F(OFF)
the
LED will remain o and no common mode failure will
occur.
The open collector drive circuit, shown in Figure 24, can
not keep the LED o during a +dV
CM
/dt transient, since
all the current owing through C
LEDN
must be supplied
by the LED, and it is not recommended for applications
requiring ultra high CMR1 performance. The alternative
drive circuit which like the recommended application
circuit (Figure 19), does achieve ultra high CMR perfor-
mance by shunting the LED in the o state.
IPM Dead Time and Propagation Delay Specications
The HCPL-J314 includes a Propagation Delay Dif-
ference (PDD) specification intended to help
designers minimize “dead time” in their power
inverter designs. Dead time is the time high and
low side power transistors are off. Any overlap
in Ql and Q2 conduction will result in large currents
flowing through the power devices from the high-
voltage to the low-voltage motor rails. To minimize dead
time in a given design, the turn on of LED2 should be
delayed (relative to the turn o of LED1) so that under
worst-case conditions, transistor Q1 has just turned o
when transistor Q2 turns on, as shown in Figure 26. The
amount of delay necessary to achieve this condition is
equal to the maximum value of the propagation delay
dierence specication, PDD max, which is specied
to be 500 ns over the operating temperature range of
-40° to 100°C.
Delaying the LED signal by the maximum propaga-
tion delay dierence ensures that the minimum dead
time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead
time is equivalent to the difference between the
maximum and minimum propagation delay dierence
specification as shown in Figure 27. The maximum
dead time for the HCPL-J314 is 1 µs (= 0.5 µs -
(-0.5 µs)) over the operating temperature range of
-40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other
and are switching identical IGBTs.
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HCPL-J314

Mfr. #:
Buy HCPL-J314
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 0.4A IGBT Gate Drive
Lifecycle:
New from this manufacturer.
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