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NCV7340D12G

P1-P3P4-P6P7-P9P10-P12
NCV7340
http://onsemi.com
4
FUNCTIONAL DESCRIPTION
Operating Modes
NCV7340 provides two modes of operation as illustrated
in Table 3. These modes are selectable through pin STB.
Table 3. OPERATING MODES
Pin
STB
Mode
Pin RXD
Low High
Low Normal Bus dominant Bus recessive
High Standby Wakeup request
detected
No wakeup
request detected
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give extremely low EME.
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are terminated to ground and supply current is reduced to a
minimum, typically 10 mA. When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
a time period of t
dwakerd
, the RxD pin is driven low by the
transceiver to inform the controller of the wake−up request.
Split Circuit
The V
SPLIT
pin is operational only in normal mode. In
standby mode this pin is floating. The V
SPLIT
can be
connected as shown in Figure 2 or, if it’s not used, can be left
floating. Its purpose is to provide a stabilized DC voltage of
0.5 x V
CC
to the bus avoiding possible steps in the
common−mode signal therefore reducing EME. These
unwanted steps could be caused by an un−powered node on
the network with excessive leakage current from the bus that
shifts the recessive voltage from its nominal 0.5 x V
CC
voltage.
Wakeup
When a valid wakeup (dominant state longer than t
Wake
)
is received during the standby mode the RxD pin is driven
low. The wakeup detection is not latched: RxD returns to
High state after t
wakedr
when the bus signal is released back
to recessive – see Figure 4. Wake−up behavior in case of a
permanent dominant − due to, for example, a bus short −
represents the only difference between the circuit functional
sub−versions listed in the Ordering Information table. When
the standby mode is entered while a dominant is present on
the bus, the “unconditioned bus wake−up” versions will
signal a bus−wakeup immediately after the state transition
(signal RxD
1
in Figure 4). The other version will signal
bus−wakeup only after the initial dominant is released
(signal RxD
2
in Figure 4). In this way it’s ensured, that a
CAN bus can be put to a low−power mode even if the nodes
have a level sensitivity to RxD pin and a permanent
dominant is present on the bus.
Figure 4. NCV7340 Wakeup Behavior
time
CANH
CANL
STB
RxD2
RxD1
normal standby
>t
Wake
<t
Wake
t
dwakerd
t
dwakedr
t
Wake(RxD)
(NCV7340−4)
(NCV7340−2, 3)
Overtemperature Detection
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 160°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
NCV7340
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5
TxD Dominant Time−out Function
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value t
dom(TxD)
, the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant time−out time (t
dom(TxD)
) defines the
minimum possible bit rate to 40 kbps.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 5). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
V
CC
supply be removed.
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (Pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Min Max Unit
V
CC
Supply voltage −0.3 +6 V
V
CANH
DC voltage at pin CANH 0 < V
CC
< 5.25 V; no time limit −50 +50 V
V
CANL
DC voltage at pin CANL 0 < V
CC
< 5.25 V; no time limit −50 +50 V
V
SPLIT
DC voltage at pin V
SPLIT
0 < V
CC
< 5.25 V; no time limit −40 +40 V
V
TxD
DC voltage at pin TxD −0.3 6 V
V
RxD
DC voltage at pin RxD −0.3 6 V
V
STB
DC voltage at pin STB −0.3 6 V
V
esd
Electrostatic discharge voltage at all pins Note 1
Note 2
−6
−500
6
500
kV
V
Electrostatic discharge voltage at CANH and CANL pins Note 3 −12 12 kV
V
schaff
Transient voltage, see Figure 5 Note 5 −150 100 V
Latchup Static latchup at all pins Note 4 120 mA
T
stg
Storage temperature −55 +150 °C
T
A
Ambient temperature −40 +125 °C
T
J
Maximum junction temperature −40 +170 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
2. Standardized charged device model ESD pulses when tested according to ESD−STM5.3.1−1999.
3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor.
4. Static latchup immunity: Static latchup protection level when tested according to EIA/JESD78.
5. Pulses 1, 2a, 3a and 3b according to ISO 7637 part 3. Verification by external test house.
Table 5. THERMAL CHARACTERISTICS
Symbol Parameter Conditions Value Unit
R
q
JA_1
Thermal Resistance Junction−to−Air, 1S0P PCB (Note 6) Free air 125 K/W
R
q
JA_2
Thermal Resistance Junction−to−Air, 2S2P PCB (Note 7) Free air 75 K/W
6. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
7. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
NCV7340
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6
Table 6. CHARACTERISTICS V
CC
= 4.75 V to 5.25 V; T
J
= −40 to +150°C; R
LT
= 60 W unless specified otherwise.
Symbol
Parameter Conditions Min Typ Max Unit
SUPPLY (Pin V
CC
)
I
CC
Supply current in normal mode Dominant; V
TxD
= 0 V
Recessive; V
TxD
= V
CC
57
7.5
75
10
mA
I
CCS
Supply current in standby mode
T
J,max
= 100°C
10 15
mA
TRANSMITTER DATA INPUT (Pin TxD)
V
IH
High−level input voltage Output recessive 2.0 − V
CC
V
V
IL
Low−level input voltage Output dominant −0.3 − +0.8 V
I
IH
High−level input current V
TxD
= V
CC
−5 0 +5
mA
I
IL
Low−level input current V
TxD
= 0 V −350 −200 −75
mA
C
i
Input capacitance Not tested − 5.0 10 pF
TRANSMITTER MODE SELECT (Pin STB)
V
IH
High−level input voltage Standby mode 2.0 − V
CC
V
V
IL
Low−level input voltage Normal mode −0.3 − +0.8 V
I
IH
High−level input current V
STB
= V
CC
−5 0 +5
mA
I
IL
Low−level input current V
STB
= 0 V −10 −4 −1
mA
C
i
Input capacitance Not tested − 5.0 10 pF
RECEIVER DATA OUTPUT (Pin RxD)
I
oh
High−level output current normal mode
V
RxD
= V
CC
– 0.4 V
−1 −0.4 −0.1 mA
I
ol
Low−level output current V
RxD
= 0.4 V 2 6 12 mA
V
oh
High−level output voltage standby mode
I
RxD
= −100 mA
V
CC
–
1.1
V
CC
–
0.7
V
CC
–
0.4
V
BUS LINES (Pins CANH and CANL)
V
o(reces)
(norm)
Recessive bus voltage on pins CANH and
CANL
V
TxD
= V
CC
; no load
normal mode
2.0 2.5 3.0 V
V
o(reces)
(stby)
Recessive bus voltage on pins CANH and
CANL
V
TxD
= V
CC
; no load
standby mode
−100 0 100 mV
I
o(reces)
(CANH)
Recessive output current at pin CANH −35 V < V
CANH
< +35 V;
0 V < V
CC
< 5.25 V
−2.5 − +2.5 mA
I
o(reces)
(CANL)
Recessive output current at pin CANL −35 V < V
CANL
< +35 V;
0 V < V
CC
< 5.25 V
−2.5 − +2.5 mA
I
LI(CANH)
Input leakage current to pin CANH V
CC
= 0 V
V
CANL
= V
CANH
= 5 V
−10 0 10
mA
I
LI(CANL)
Input leakage current to pin CANL V
CC
= 0 V
V
CANL
= V
CANH
= 5 V
−10 0 10
mA
V
o(dom)
(CANH)
Dominant output voltage at pin CANH V
TxD
= 0 V 3.0 3.6 4.25 V
V
o(dom)
(CANL)
Dominant output voltage at pin CANL V
TxD
= 0 V 0. 5 1.4 1.75 V
V
o(dif)
(bus_dom)
Differential bus output voltage (V
CANH
−
V
CANL
)
V
TxD
= 0 V; dominant;
42.5 W < R
LT
< 60 W
1.5 2.25 3.0 V
V
o(dif)
(bus_rec)
Differential bus output voltage (V
CANH
−
V
CANL
)
V
TxD
= V
CC
; recessive; no
load
−120 0 +50 mV
I
o(sc)
(CANH)
Short circuit output current at pin CANH for
the NCV7340D13(R2)G
V
CANH
= 0 V; V
TxD
= 0 V −100 −70 −45 mA
Short circuit output current at pin CANH for
NCV7340D12(R2)G & NCV7340D14(R2)G
V
CANH
= 0 V; V
TxD
= 0 V −120 −70 −45 mA
P1-P3P4-P6P7-P9P10-P12

NCV7340D12G

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Buy NCV7340D12G
Manufacturer:
ON Semiconductor
Description:
IC HS CAN TRANSC 8SOIC
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