MC100LVEL16DTG

© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 7
1 Publication Order Number:
MC100LVEL16/D
MC100LVEL16
3.3V ECL Differential
Receiver
Description
The MC100LVEL16 is a differential receiver. The device is
functionally equivalent to the EL16 device, operating from a 3.3 V
supply. The LVEL16 exhibits a wider V
IHCMR
range than its EL16
counterpart. With output transition times and propagation delays
comparable to the EL16 the LVEL16 is ideally suited for interfacing
with high frequency sources at 3.3 V supplies.
Under open input conditions, the Q input will be pulled down to V
EE
and the Q input will be biased to V
CC
/2. This condition will force the
Q output low.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
300 ps Propagation Delay
High Bandwidth Output Transitions
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −3.8 V
Internal Input Pulldown Resistors on D, Pullup and Pulldown
Resistors on D
Q Output will Default LOW with Inputs Open or at V
EE
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
KV16
ALYWG
G
SOIC−8
D SUFFIX
CASE 751
1
8
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
www.
onsemi.com
KVL16
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
(Note: Microdot may be in either location)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
4BMG
G
1
MC100LVEL16
www.onsemi.com
2
Figure 1. Logic Diagram and Pinout Assignment
D, D ECL Data Inputs
Q, Q
ECL Data Outputs
V
BB
Reference Voltage Output
V
CC
Positive Supply
V
EE
Negative Supply
NC No Connect
Table 1. PIN DESCRIPTION
PIN FUNCTION
1
2
3
45
6
7
8
Q
V
EE
V
CC
D
Q
D
V
BB
NC
EP
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
75 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 4 KV
> 400 V
> 2 kV
Moisture Sensitivity, Indefinite Time out of Drypack,
Pb−Free Packages (Note 1) SOIC−8
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 79
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Refer to Application Note AND8003/D for additional information.
MC100LVEL16
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3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 8 to 0 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −8 to 0 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
6 to 0
−6 to 0
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
I
BB
V
BB
Sink/Source ± 0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 LFPM
500 LFPM
SO−8
SO−8
190
130
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board SO−8 41 to 44 ± 5% °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 LFPM
500 LFPM
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder Pb
Pb−Free
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
q
JC
Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

MC100LVEL16DTG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Bus Receivers 3.3V ECL Diff
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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