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A4975SLBTR-T

P1-P3P4-P6P7-P9P10-P12P13-P13
Full-Bridge PWM Microstepping Motor Driver
A4975
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Control Circuitry (cont’d)
Current-Sense Comparator Input
Offset Voltage*
V
IO(S)
V
REF
= 0 V — — ±5.0 mV
Step Reference Current Ratio SRCR
D
0
= D
1
= D
2
= V
IN(0)
—0—%
D
0
= V
IN(1)
, D
1
= D
2
= V
IN(0)
— 19.5 — %
D
0
= V
IN(0)
, D
1
= V
IN(1)
, D
2
= V
IN(0)
— 38.2 — %
D
0
= D
1
= V
IN(1)
, D
2
= V
IN(0)
— 55.5 — %
D
0
= D
1
= V
IN(0)
, D
2
= V
IN(1)
— 70.7 — %
D
0
= V
IN(1)
, D
1
= V
IN(0)
, D
2
= V
IN(1)
— 83.1 — %
D
0
= V
IN(0)
, D
1
= D
2
= V
IN(1)
— 92.4 — %
D
0
= D
1
= D
2
= V
IN(1)
— 100 — %
Thermal Shutdown Temp. T
J
— 165 — °C
Thermal Shutdown Hysteresis T
J
—15—°C
AC Timing
PWM RC Fixed Off-time t
OFFRC
C
T
= 470 pF, R
T
= 43 k 18.2 20.2 22.3 s
PWM Minimum On Time t
ON(min)
V
CC
= 5.0 V, R
T
43 k, C
T
= 470 pF,
I
OUT
= 100 mA
0.8 1.6 2.2 s
ELECTRICAL CHARACTERISTICS (continued) at T
A
= 25°C, V
CC
= 4.5 to 5.5 V (unless
otherwise noted.)
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
* The total error for the V
REF
/V
S
function is the sum of the D/A error and the current-sense comparator input offset voltage.
Table 3 — DAC Truth Table
DAC DATA Current
D
2
D
1
D
0
Ratio, % V
REF
/V
S
H H H 100 5.00
H H L 92.4 5.41
H L H 83.1 6.02
H L L 70.7 7.07
L H H 55.5 9.01
L H L 38.2 13.09
L L H 19.5 25.64
L L L All Outputs Disabled
where V
S
= I
TRIP
×R
S
. See Applications section.
Table 1 — PHASE Truth Table
PHASE OUT
A
OUT
B
H H L
L L H
Table 2 — PFD Truth Table
V
PFD
Description
3.5 V Slow Current-Decay Mode
1.1 V to 3.1 V Mixed Current-Decay Mode
0.8 V Fast Current-Decay Mode
Full-Bridge PWM Microstepping Motor Driver
A4975
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal Functions
Terminal Name Description
1 PFD (Percent Fast Decay) The analog input used to set the current-decay mode.
2 REF (V
REF
) The voltage at this input (along with the value of R
S
and the states of DAC inputs
D
0
, D
1
, and D
2
) set the peak output current.
3 RC The parallel combination of external resistor R
T
and capacitor C
T
set the off time for the
PWM current regulator. C
T
also sets the blanking time.
4-5 GROUND Return for the logic supply (V
CC
) and load supply (V
BB
); the reference for all voltage
measurements.
6 LOGIC SUPPLY (V
CC
) Supply voltage for the logic circuitry. Typically = 5 V.
7 PHASE The PHASE input determines the direction of current in the load.
8 D
2
(DATA
2
) One-of-three (MSB) control bits for the internal digital-to-analog converter.
9 D
1
(DATA
1
) One-of-three control bits for the internal digital-to-analog converter.
10 OUT
A
One-of-two output load connections.
11 SENSE Connection to the sink-transistor emitters. Sense resistor R
S
is connected between this
point and ground.
12-13 GROUND Return for the logic supply (V
CC
) and load supply (V
BB
); the reference for all voltage
measurements.
14 D
0
(DATA
0
) One-of-three (LSB) control bits for the internal digital-to-analog converter.
15 OUT
B
One-of-two output load connections.
16 LOAD SUPPLY (V
BB
) Supply voltage for the load.
Note the A4975SB (DIP) and the A4975SLB
(SOIC) are electrically identical and share a
common terminal number assignment.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GROUND
GROUND
LOGIC
SUPPLY
PHASE
GROUND
GROUND
RC
SENSE
D
REF
LOAD
SUPPLY
V
CC
OUT
B
OUT
A
V
BB
LOGIC
PFD
1
D
0
D
2
Full-Bridge PWM Microstepping Motor Driver
A4975
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Two A4975 full-bridge PWM microstepping motor drivers are
needed to drive the windings of a bipolar stepper motor. Internal
pulse width modulated (PWM) control circuitry regulates each
motor winding current. The peak motor current is set by the
value of an external current-sense resistor (R
S
), a reference
voltage (V
REF
), and the digital-to-analog converter (DAC) data
inputs (D
0
, D
1
, and D
2
).
To improve motor performance, especially when using
sinusoidal current profi les necessary for microstepping, the
A4975 has three distinct current-decay modes: slow decay, fast
decay, and mixed decay.
PHASE Input. The PHASE input controls the direction of
current fl ow in the load (table 1). An internally generated dead
time of approximately 500 ns prevents crossover currents that
could occur when switching the PHASE input.
DAC Data Inputs (D
0
, D
1
, D
2
). A non-linear DAC is used
to digitally control the output current. The output of the DAC is
used to set the trip point of the current-sense comparator. Table 3
shows DAC output voltages for each input condition. When D
0
,
D
1
, and D
2
are all logic low, all of the power output transistors
are turned off.
Internal PWM Current Control. Each motor driver
contains an internal fi xed off-time PWM current-control circuit
that limits the load current to a desired value (I
TRIP
). Initially,
a diagonal pair of source and sink transistors are enabled and
current fl ows through the motor winding and R
S
(fi gure 1). When
the voltage across the sense resistor equals the DAC output
voltage the current-sense comparator resets the PWM latch,
which turns off the source drivers (slow-decay mode) or the sink
and source drivers (fast- or mixed-decay mode).
With the DAC data input lines at V
IN(1)
voltage, the maximum
value of current limiting is set by the selection of R
S
and V
REF
with a transconductance function approximated by:
I
TRIP
≈ V
REF
/ 5R
S
.
The actual peak load current (I
PEAK
) will be slightly higher than
I
TRIP
due to internal logic and switching delays. The driver(s)
remain off for a time period determined by a user-selected
external resistor-capacitor combination (R
T
C
T
). At the end of
the fi xed off-time, the driver(s) are re-enabled, allowing the load
current to increase to I
TRIP
again, maintaining an average load
current.
The DAC data input lines are used to provide up to eight levels
of output current. The internal 3-bit digital-to-analog converter
reduces the reference input to the current-sense comparator
in precise steps (the step reference current ratio or SRCR) to
provide half-step, quarter-step, or “microstepping” load-current
levels.
I
TRIP
≈ SRCR x V
REF
/ 5R
S
Slow Current-Decay Mode. When V
PFD
≥ 3.5 V, the
device is in slow current-decay mode (the source drivers are
disabled when the load current reaches I
TRIP
). During the fi xed
off-time, the load inductance causes the current to recirculate
through the motor winding and sink drivers (see fi gure 1).
Slow-decay mode produces low ripple current for a given fi xed
off-time (see fi gure 2). Low ripple current is desirable because
the average current in the motor winding is more nearly equal
to the desired reference value, resulting in increased motor
Figure 1 — Load-Current Paths
PFD
Dwg. WP-031-1
t
I
PEAK
OFF
SLOW (V ≥ 3.5 V)
PFD
MIXED (1.1 V ≤ V ≤ 3.1 V)
FAST (V ≤ 0.8 V)
PFD
PFD
Figure 2 — Current-Decay Waveforms
R
S
V
BB
Drive Current (Normal)
Recirculation (Fast Decay)
Recirculation (Slow Decay)
P1-P3P4-P6P7-P9P10-P12P13-P13

A4975SLBTR-T

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Microstepping Motor Driver 16-Pin SOIC T/R
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