GTLP10B320MTDX

© 2001 Fairchild Semiconductor Corporation DS500483 www.fairchildsemi.com
May 2001
Revised May 2001
GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
GTLP10B320
10-Bit LVTTL/GTLP Transceiver
with Split LVTTL Port and Feedback Path
General Description
The GTLP10B320 is a 10-bit Universal bus driver and
receiver, with separate LVTTL inputs and outputs and a
feedback path for diagnostics, that provides LVTTL to
GTLP signal level translation. High speed backplane oper-
ation is a direct result of GTLP’s reduced output swing
(
<1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the
Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output low level is typ-
ically less than 0.5V, the output level high is 1.5V and the
receiver threshold is 1.0V.
Features
Bidirectional interface between GTLP and LVTTL logic
levels
Variable edge rate control pin to select desired edge rate
on GTLP port (V
ERC
)
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
Split LVTTL inputs and outputs
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
A feedback path for control and diagnostics monitoring
TTL compatible driver and control inputs
Designed using Fairchild advanced BiCMOS technology
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
Power up/down and power off high impedance for live
insertion
Open drain on GTLP to support wired-or connection
Flow through pinout optimizes PCB layout
A Port source/sink
24mA/+24mA
B Port sink
+50mA
Ordering Code:
Device is also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Order Number Package Number Package Description
GTLP10B320MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com 2
GTLP10B320
Pin Descriptions Connection Diagram
Functional Description
The GTLP10B320 is a 10-bit Universal driver and receiver
containing D-Type flip-flop, latch, and transparent modes of
operation for the data paths. In addition there is an internal
feedback path that can be used for diagnostic monitoring or
caching schemes. Data flow in each direction is controlled
by the clock signals (LECLKAB and LECLKBC) and output
enables (OEB
and OEC). The internal feedback path is
controlled by the SEL
pin and allows data transfer from
Port A to Port C without requiring data to be output to the
backplane. The internal feedback path is selected with SEL
LOW and the B Port pin is selected with SEL HIGH. The
data paths can also be configured for latch/transparent or
register mode for each direction with the SAB and SBC
pins. Data polarity is non-inverting with the GTLP outputs
enabled via the OEB
pin and the LVTTL outputs being
enabled via the OEC
pin.
For A-to-B data flow the device is configured into a latch/
transparent or register mode by pin SAB. If SAB is LOW
then the register mode is selected and the device operates
on the LOW-to-HIGH transition of LECLKAB. If SAB is
HIGH then the latch/transparent configuration is selected
and a HIGH-to-LOW transition of LECLKAB stores data in
the latch. If LECLKAB is HIGH the device is in transparent
mode. When OEB
is LOW the outputs are active and when
OEB
is HIGH the outputs are high impedance.
Pin Names Description
OEB
, OEC B Port, C Port Output Enable
respectively (Active LOW)
V
CC
, GND, V
REF
Device Supplies
LECLKAB,
LECLKBC
A-to-B, B-to-C Latch CLK
respectively
(Transparent Active HIGH)
SEL
Selects Internal Feedback Path
SAB, SBC Selects Register or Latch/Transparent
Path for A-to-B and B-to-C respectively
B
0
-B
9
B Port GTLP I/O
A
0
-A
9
A Port LVTTL Inputs
C
0
-C
9
C Port LVTTL Outputs
V
ERC
Edge Rate Control Pin
(GND
= Slow Edge Rate)
(V
CC
= Fast Edge Rate)
3 www.fairchildsemi.com
GTLP10B320
Functional Tables
Note 1: Output level before the indicated steady state input conditions were established.
Note 2: The data flow of B-to-C is similar except that OEC
, SBC and LECLKBC are used.
Note 3: Function identical for SEL
= 1 if timing requirements for propagation delay to output and set-up to LECLKBC are met at B Port.
Note 4: Output level before the indicated steady state input conditions were established.
I/O Path: SEL = 1 (External Feedback Path) (Note 2)
Inputs Outputs
OEB OEC SAB SBC LECLKAB LECLKBC Mode
(AB)
A
n
C
n
B
n
010X XRegisterLX L
010X
XRegisterHX H
010X L X Register L XB
0
(Note 1)
010X L X Register H XB
0
(Note 1)
011X
X Latch L X L
011X H X Buffer L X L
011X
X Latch H X H
011X H X Buffer H X H
1 1 X X X X High Impedance X X Z
Internal Feedback Path: SEL
= 0 (Internal Feedback Path) (Note 3)
Inputs Outputs
OEB OEC SAB SBC LECLKAB LECLKBC Mode
(AB/BC)
A
n
B
n
C
n
0000 ↑↑Register/Register L L L
0000
↑↑Register/Register H H H
0000 L
Register/Register X B
0
(Note 4) B
0
(Note 4)
0000
L Register/Register L L B
0
(Note 4)
0000
L Register/Register H H B
0
(Note 4)
0000 L LRegister/RegisterXB
0
(Note 4) B
0
(Note 4)
0001
↑↓Register/Latch L L L
0001
H Register/Buffer L L L
0001
↑↓Register/Latch H H H
0001
H Register/Buffer H H H
0001 L
Register/Latch X B
0
(Note 4) B
0
(Note 4)
0001 L HRegister/BufferXB
0
(Note 4) B
0
(Note 4)
0001 L LRegister/LatchXB
0
(Note 4) B
0
(Note 4)
0010
↓↑Latch/Register L L L
0010
↓↑Latch/Register H H H
0010
L Latch/Register L L B
0
(Note 4)
0010
L Latch/Register H H B
0
(Note 4)
0010 H
Buffer/Register L L L
0010 H
Buffer/Register H H H
0010 L LLatch/RegisterXB
0
(Note 4) B
0
(Note 4)
0011
↓↓Latch/Latch L L L
0011
↓↓Latch/Latch H H H
0011 H HBuffer/BufferL L L
0011 H HBuffer/BufferH H H
1 1 X X X X High Impedance X Z Z

GTLP10B320MTDX

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Bus Transceivers 10-Bit Transceiver LVTTL/GTLP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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