AD9850
–5–
REV. H
PIN CONFIGURATION
17
16
15
20
19
18
28
27
26
25
24
23
22
21
14
13
12
11
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD9850
D3
D7 MSB/SERIAL LOAD
D6
D5
D4
D2
D1
LSB D0
RESET
DVDD
DGND
DGND
DVDD
W
CLK
FQ
UD
CLKIN
AGND AGND
IOUTB
IOUT
AVDD
R
SET
QOUTB
QOUT
AVDD
VINN
VINP
DACBL (NC)
NC = NO CONNECT
Table I. PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
4 to 1, D0 to D7 8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase/
28 to 25 control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data-word.
5, 24 DGND Digital Ground. These are the ground return leads for the digital circuitry.
6, 23 DVDD Supply Voltage Leads for Digital Circuitry.
7W_CLK Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.
8 FQ_UD Frequency Update. On the rising edge of this clock, the DDS updates to the frequency (or phase)
loaded in the data input register; it then resets the pointer to Word 0.
9 CLKIN Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at
1/2 V supply. The rising edge of this clock initiates operation.
10, 19 AGND Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).
11, 18 AVDD Supply Voltage for the Analog Circuitry (DAC and Comparator).
12 R
SET
DAC’s External R
SET
Connection. This resistor value sets the DAC full-scale output current. For
normal applications (F
S
I
OUT
= 10 mA), the value for R
SET
is 3.9 kΩ connected to ground. The R
SET
/I
OUT
relationship is I
OUT
= 32 (1.248 V/R
SET
).
13 QOUTB Output Complement. This is the comparator’s complement output.
14 QOUT Output True. This is the comparator’s true output.
15 VINN Inverting Voltage Input. This is the comparator’s negative input.
16 VINP Noninverting Voltage Input. This is the comparator’s positive input.
17 DACBL (NC) DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should
normally be considered a no connect for optimum performance.
20 IOUTB Complementary Analog Output of the DAC.
21 IOUT Analog Current Output of the DAC.
22 RESET Reset. This is the master reset function; when set high, it clears all registers (except the input register), and
the DAC output goes to cosine 0 after additional clock cycles—see Figure 7.
