96SD2-512M667NN-TR

T
T
T
S
S
S
6
6
6
Q
Q
Q
S
S
S
J
J
J
2
2
2
3
3
3
0
0
0
0
0
0
2
2
2
-
-
-
6
6
6
S
S
S
200PIN DDR2 667 SO-DIMM
512MB With 64Mx8 CL5
Transcend Information Inc.
SERIAL PRESENCE DETECT SPECIFICATION
Serial Presence Detect
Byte No.
Function Described Standard Specification
Vendor Part
0
# of Serial PD Bytes written during module production
128bytes 80
1 Total # of Bytes of S.P.D Memory Device 256bytes 08
2 Fundamental Memory Type DDR2 SDRAM 08
3 # of Row Addresses on this Assembly 14 0E
4 # of Column Addresses on this Assembly 10 0A
5 # of Module Rows on this Assembly
1 ROW, Planar,
30.0mm
60
6 Data Width of this Assembly 64bits 40
7
Reserved
- 00
8 VDDQ and Interface Standard of this Assembly SSTL 1.8V 05
9
DDR2 SDRAM cycle time at Max. Supported CAS
latency=X
3.0ns 30
10
DDR2 SDRAM Access time from clock at CL=X
0.45ns
45
11 DIMM configuration type (non-parity, Parity, ECC) Non ECC 00
12 Refresh Rate 7.8us 82
13 Primary DDR2 SDRAM Width X8 08
14 Error Checking DDR2 SDRAM Width N/A 00
15 Reserved - 00
16
DDR2 SDRAM device attributes: Burst lengths
supported
4,8 0C
17
DDR2 SDRAM device attributes: # of banks on each
DDR2 SDRAM device
4 banks 04
18
DDR2 SDRAM device attributes:CAS Latency
supported
5,4,3 38
19 DIMM Mechanical characteristics; thickness
01
20
DIMM type information
SODIMM 04
21 DDR2 SDRAM Module Attributes
Analysis probe not
installed, FET switch
external not enable
00
22 DDR2 SDRAM Device Attributes: General Supports weak driver 07
23 DDR2 SDRAM Cycle Time CL=X-1 3.75ns 3D
24 DDR SDRAM Access from Clock CL=X-1
0.5ns
50
25 DDR SDRAM Cycle Time CL=X-2 5.0ns 50
26 DDR SDRAM Access from Clock CL=X-2
0.6ns
60
27 Minimum Row Precharge Time (tRP) 15ns 3C
28 Minimum Row Active to Row Activate delay (tRRD) 7.5ns 1E
29 Minimum RAS to CAS Delay (tRCD) 15ns 3C
30 Minimum active to Precharge time (tRAS) 39ns 27
31 Module ROW density 512MB 80
32
Command and address setup time before clock(=tIS)
0.20ns 20
33
Command and address hold time after clock(=tIH)
0.27ns 27
34
Data input setup time before strobe(=tDS)
0.10ns 10
35
Data input hold time after strobe(=tDH)
0.17ns 17
T
T
T
S
S
S
6
6
6
Q
Q
Q
S
S
S
J
J
J
2
2
2
3
3
3
0
0
0
0
0
0
2
2
2
-
-
-
6
6
6
S
S
S
200PIN DDR2 667 SO-DIMM
512MB With 64Mx8 CL5
Transcend Information Inc.
36
Write recovery time(=tWR)
15ns 3C
37
Internal write to read command delay(=tWTR)
7.5ns 1E
38
Internal read to precharge command delay(=tRTP)
7.5ns 1E
39
Memory analysis probe characteristics
- 00
40
Reserved
- 00
41
DDR SDRAM Minimum Active to Active/Auto Refresh
Time(tRC)
54ns 36
42
DDR SDRAM Minimum Auto-Refresh to
Active/Auto-Refresh Command Period (tRFC)
105ns 69
43
DDR SDRAM Maximum Device Cycle Time (tCK max)
8ns 80
44
DDR SDRAM DQS-DQ Skew for DQS and associated
DQ signals (tDQSQ max)
0.24ns 18
45
DDR SDRAM Read Data Hold Skew Factor (tQHS)
0.34ns 22
46
PLL Relock Time
- 00
47~61
Superset Information
- 00
62 SPD Data Revision Code REV 1.2 12
63 Checksum for Bytes 0-62 6B 6B
64-71 Manufacturers JEDEC ID Transcend 01, 4F
72 Manufacturing Location T 54
54
53
36
34
4D
53
51
36
34
56
36
4A
73-90 Manufacturers Part Number TS64MSQ64V6J
20
20
20
20
20
20
91-92 Revision Code - -
93-94 Manufacturing Date By Manufacturer Variable
95-98 Assembly Serial Number By Manufacturer Variable
99-127 Manufacturer Specific Data - -
128~255
Open for customer use
Undefined -

96SD2-512M667NN-TR

Mfr. #:
Manufacturer:
Advantech
Description:
Memory Modules 512M SO-DDR2-667 200PIN 64X8 SAM(G)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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