OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

96SD2-512M667NN-TR

P1-P3P4-P6P7-P9P10-P11
T
T
T
S
S
S
6
6
6
Q
Q
Q
S
S
S
J
J
J
2
2
2
3
3
3
0
0
0
0
0
0
2
2
2
-
-
-
6
6
6
S
S
S
200PIN DDR2 667 SO-DIMM
512MB With 64Mx8 CL5
Transcend Information Inc.
Input AC Logic Level
Parameter Symbol Min Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.250 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.250 V
AC Input Test Condition
Condition Symbol Value Unit Note
Input reference voltage V
REF
0.5*VDDQ V 1
Input signal maximum peak to peak swing V
SWING
(
MAX
) 1.0 V 1
Input signal minimum slew rate SLEW
1.0 V/ns 2,3
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the
device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising
edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure.
Note:
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions
and VIH(AC) to VIL(AC) on the negative transitions.
V
delta TF
delta TR
Falling Slew=
V -V (AC)
delta TF
Rising Slew=
V (AC) V
delta TR
AC Input Test Signal Waveform
Input/Output Capacitance
(V
DD
= 1.8V, V
DDQ
= 1.8V, T
A
= 25°
°°
°C)
Parameter Symbol Min Max Unit
Input capacitance (CK0 and /CK0)
Input capacitance (CK1 and /CK1)
Input capacitance (CKE0 and /CS)
Input capacitance (A0~A15, BA0~BA2, /RAS, /CAS, /WE)
Input capacitance (DQ, DM, DQS, /DQS)
CCK0
CCK1
CI
1
CI
2
CIO
-
-
-
-
-
26
28
42
42
10
pF
pF
pF
pF
pF
Note:
DM is internally loaded to match DQ and DQS identically.
T
T
T
S
S
S
6
6
6
Q
Q
Q
S
S
S
J
J
J
2
2
2
3
3
3
0
0
0
0
0
0
2
2
2
-
-
-
6
6
6
S
S
S
200PIN DDR2 667 SO-DIMM
512MB With 64Mx8 CL5
Transcend Information Inc.
Timing Parameters & Specifications
(These AC characteristics were tested on the Component)
Parameter Symbol Min Max Unit Note
DQ output access time from CK & /CK
tAC
-450 +450 ps
DQS output access time from CK & /CK tDQSCK -400 +400 ps
CK high-level width
tCH 0.45 0.55 tCK
CK low-level width tCL 0.45 0.55 tCK
CK half period
tHP min(tCL,tCH) X
ps
Clock cycle time, CL=x
tCK 3000 8000 ps
DQ and DM input hold time
tDH 300 x
ps
DQ and DM input setup time
tDS 100 X ps
Control & Address input pulse width for each input
tIPW 0.6 x tCK
DQ and DM input pulse width for each input
tDIPW 0.35 X tCK
Data-out high-impedance time from CK/CK
tHZ X
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min tAC max ps
DQ low-impedance time from CK/CK
tLZ(DQ) 2*TAC min TAC max
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ X 240 ps
DQ hold skew factor
tQHS X 340
ps
DQ/DQS output hold time from DQS
tQH tHP - tQHS X ps
Write command to first DQS latching transition
tDQSS WL-0.25 WL+0.25 tCK
DQS input high pulse width
tDQSH 0.35 X tCK
DQS input low pulse width
tDQSL 0.35 X tCK
DQS falling edge to CK setup time
tDSS
0.2 X
tCK
DQS falling edge hold time from CK
tDSH 0.2 X tCK
Mode register set command cycle time
tMRD 2 X tCK
Write postamble
tWPST 0.4 0.6 tCK
Write preamble
tWPRE 0.35 X tCK
Address and control input hold time
tIH 400 X
ps
Address and control input setup time
tIS 200 X ps
Read preamble
tRPRE 0.9 1.1 tCK
Read postamble
tRPST 0.4 0.6 tCK
Active to active command period for 1KB page size
products
tRRD 7.5 X ns
Active to active command period for 2KB page size
products
tRRD 10 X ns
Four Activate Window for 1KB page size products
tFAW 37.5 ns
Four Activate Window for 2KB page size products
tFAW 50 ns
T
T
T
S
S
S
6
6
6
Q
Q
Q
S
S
S
J
J
J
2
2
2
3
3
3
0
0
0
0
0
0
2
2
2
-
-
-
6
6
6
S
S
S
200PIN DDR2 667 SO-DIMM
512MB With 64Mx8 CL5
Transcend Information Inc.
/CAS to /CAS command delay
tCCD
2 tCK
Write recovery time tWR
15 X
ns
Auto precharge write recovery + precharge time tDAL tWR+tRP
X tCK
Internal write to read command delay tWTR
10 X ns
Internal read to precharge command delay tRTP
7.5
ns
Exit self refresh to a non-read command tXSNR tRFC + 10
ns
Exit self refresh to a read command tXSRD
200 tCK
Exit precharge power down to any non-read command tXP
2 X
tCK
Exit active power down to read command tXARD
2 X tCK
Exit active power down to read command (Slow exit,
Lower power)
tXARDS 7 - AL
tCK
CKE minimum pulse width (high and low pulse width) tCKE
3 tCK
ODT turn-on delay tAOND
2 2 tCK
ODT turn-on tAON tAC(min) tAC(max)+0.7
ns
ODT turn-on(Power-Down mode) tAONPD tAC(min)+2
2tCK+
tAC(max)+1
ns
ODT turn-off delay tAOFD
2.5 2.5 tCK
ODT turn-off tAOF tAC(min) tAC(max)+ 0.6
ns
ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2
2.5tCK+
tAC(max)+1
ns
ODT to power down entry latency tANPD
3 tCK
ODT power down exit latency tAXPD
8 tCK
OCD drive mode output delay tOIT
0 12 ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay tIS+tCK+tIH
ns
P1-P3P4-P6P7-P9P10-P11

96SD2-512M667NN-TR

Mfr. #:
Buy 96SD2-512M667NN-TR
Manufacturer:
Advantech
Description:
Memory Modules 512M SO-DDR2-667 200PIN 64X8 SAM(G)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet