The Smart Timing Choice
The Smart Timing Choice
SiTime Corporation 990 Almanor Avenue Sunnyvale, CA 94085 (408) 328-4400 www.sitime.com
Rev. 1.2 Revised July 24, 2014
SiT3907
High Precision Digitally Controlled Oscillator (DCXO)
Notes:
1. Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage.
2. APR = pull range (PR) - frequency stability (F_stab) - Aging (F_aging)
Features Applications
Factory programmable between 1 MHz and 220 MHz Ideal for clock synchronization, instrumentation, low
bandwidth PLL, jitter cleaner, clock recovery, audio,
video, and FPGA
Digitally controlled pull range: ±25, ±50, ±100, ±200, ±400, ±800,
±1600 PPM
Eliminate the need for an external DAC
Superior pull range linearity of <= 0.01%
LVCMOS/LVTTL compatible output
Three industry-standard packages: 3.2 mm x2.5 mm (4-pin), 5.0 mm
x 3.2 mm (6-pin), 7.0 mm x 5.0 mm (6-pin)
Programmable drive strength to reduce EMI
Outstanding silicon reliability of 2 FIT
Electrical Characteristics
Parameters Symbol Min. Typ. Max. Unit Condition
Output Frequency Range f 1 – 220 MHz
Frequency Stability
F_stab
-10 – +10 PPM
Inclusive of initial tolerance, operating temperature, rated
power, supply voltage and load change-25 – +25 PPM
-50 – +50 PPM
Aging F_aging -5 – +5 PPM 10 years
Operating Temperature Range T_use
-20 – +70 °C Extended Commercial
-40 – +85 °C Industrial
Supply Voltage Vdd
1.71 1.8 1.89 V
2.25 2.5 2.75 V
2.52 2.8 3.08 V
2.97 3.3 3.63 V
Pull Range PR
±25, ±50, ±100, ±200
±400, ±800, ±1600
PPM See the last page for Absolute Pull Range, APR table
Linearity Lin – – 0.01 %
Frequency Change Polarity – Positive Slope –
Frequency Update Rate F_update – – 25 kU / s Frequency control mode 1, see Table 1
– – 12.5 kU / s Frequency control mode 2, see Table 2
Current Consumption Idd – 32 34 mA No load condition, f = 100 MHz, Vdd = 2.5V, 2.8V or 3.3V
– 31 34 mA No load condition, f = 100 MHz, Vdd = 1.8 V
Duty Cycle DC 45 – 55 % Vdd = 1.8V, 2.5V, 2.8V or 3.3V
Rise/Fall Time Tr, Tf – 1.2 2 ns Vdd =1.8V, 2.5V, 2.8V or 3.3V, 10% - 90% Vdd level
Output High Voltage VOH 90 – – %Vdd IOH = -6mA, Vdd = 3.3V, 2.8V, 2.5V
IOL = -3mA, Vdd = 1.8V
Output Low Voltage VOL – – 10 %Vdd IOH = -6mA, Vdd = 3.3V, 2.8V, 2.5V
IOL = -3mA, Vdd = 1.8V
Output Load Ld – – 15 pF
Start-up Time T_start – 6 10 ms
Input Low Voltage VIL – – 0.2xVdd V See Figure 5
Input Middle Voltage VIM 0.4xVdd – 0.6xVdd V See Figure 5
Input High Voltage VIH 0.8xVdd – – V See Figure 5
Input High or Low Logic Pulse T_logic 500 – – ns See Figure 5
Input Middle Pulse Width T_middle 500 – – ns See Figure 5
Input Impedance Zin 100 – – kΩ
Input Capacitance Cin – 5 – pF 20% to 80%
RMS period Jitter T_jitt – 1.5 2 ps f = 20 MHz, all Vdds
– 2 3 ps f = 20 MHz, all Vdds
RMS Phase Jitter (random) T_phj – 0.6 1 ps f = 20 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdds. No activity on DP pin.
– 0.65 1 ps With full activity on DP pin.
