Document Number: 001-15599 Rev. *E Page 3 of 9
VCXO and VIN
The output frequency of the device is adjusted over a limited
range by use of the VCXO feature. This feature is typically used
to phase and frequency lock to a separate reference clock. The
frequency is controlled by the analog voltage on the VIN pin. The
nominal output frequency is generated when VIN = 1.65V. As the
voltage on VIN is increased, the output frequency increases. The
voltage range for VIN is from 0V (V
SS
) to V
DD
.
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise on the power supply
pins degrade device performance. For general power plane
decoupling, make certain there is at least one tantalum capacitor
(~5 to 10 μF) in the general vicinity of this device. Additionally,
ensure one or two multi-layer ceramic chip capacitors (0.01 or
0.1 μF) is located as close as possible to the power and ground
pins of the device. Make certain to optimize the layout to
minimize power and ground inductance and to locate the
capacitor as close to the device pins as possible.
Termination for LVDS Output
Use a 100Ω terminating resistor to terminate CLK and CLK# with
two parallel differential traces split near the driver; connect the
resistors between each pair near the receiver. This is shown in
the following figure.
Figure 2. LVDS Output Termination
Crystal Input Interface
The CY2VC521-2 is designed for use with a 14 pF parallel
resonant crystal. This assumes 2 pF of board capacitance on
each crystal signal traces, plus 26 pF internally on both the XIN
and XOUT pins. The crystal is required to meet the parameters
shown in “Crystal Characteristics” on page 4. Because the
frequency pulling function is implemented inside the PLL, there
are no additional requirements placed on the crystal for
pullability.
The design may require external trimming capacitors if the
crystal has C
L
greater than 14 pF, depending on the layout.
VIN Control
Figure 3 shows a typical VCXO control curve for the
CY2VC521-2. The conditions are 25°C, V
DD
=3.3V, crystal
C
L
=13 pF, and board capacitance on XIN and XOUT traces of
3.5 pF each. Note that the internal capacitance measured on the
XIN and XOUT pins is approximately 26 pF.
In this case the curve is not centered (0 ppm at VIN=V
DD
/2)
because the capacitive loading on the crystal is too high, which
causes it to oscillate slower than its nominal frequency. When the
crystal is capacitively loaded as specified (C
L
), it oscillates at its
specified frequency, and the VCXO control curve is nominally
centered. Such changes in the crystal oscillation frequency result
in a vertical shift of the curve. The slope and linearity of the curve
are independent of the crystal characteristics.
Figure 3. Typical VCXO Control Curve
Frequency Table
Inputs
Output Frequency (MHz)
Xtal Frequency (MHz) PLL Multiplier Value
27 8 216
Z0 = 50Ω
100Ω
IN
Z0 = 50Ω
Z0 = 50Ω
100Ω
IN
Z0 = 50Ω
CLK
CLK#
-250
-200
-150
-100
-50
0
50
100
150
0 0.5 1 1.5 2 2.5 3 3.5
VIN Voltage
PPM from 216MHz
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