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CY2VC521ZXC-2T

P1-P3P4-P6P7-P9
CY2VC521-2
Document Number: 001-15599 Rev. *E Page 4 of 9
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
V
DD
Supply Voltage –0.5 4.4 V
V
IN
[1]
Input Voltage, DC Relative to V
SS
–0.5 V
DD
+0.5 V
T
S
Temperature, Storage Non Operating –65 150 °C
T
J
Temperature, Junction – 135 °C
ESD
HBM
ESD Protection (Human Body Model) JEDEC STD 22-A114-B 2000 – V
UL–94 Flammability Rating At 1/8 in. V–0
Θ
JA
[5]
Thermal Resistance, Junction to Ambient 0 m/s airflow 84 °C/W
1 m/s airflow 79
2.5 m/s airflow 76
Operating Conditions
Parameter Description Min Typ Max Unit
V
DD
Supply Voltage Range 3.15 3.3 3.45 V
T
PU
Power up time for V
DD
to reach V
DD
(min). (Ensure power ramp is monotonic.) 0.05 – 500 ms
T
A
Ambient Temperature 0 – 70 °C
Crystal Characteristics
Parameter Description Min Typ Max Unit
Mode of Oscillation Fundamental
F Frequency –27–MHz
C
L
Load Capacitance – 14 – pF
ESR Equivalent Series Resistance – – 50 Ω
C
S
Shunt Capacitance – – 7 pF
DC Electrical Characteristics
Parameter Description Condition Min Typ Max Unit
I
DD
[3]
Power Supply Current Outputs on and terminated – – 120 mA
V
OD
LVDS Differential Output Voltage 247 350 454 mV
ΔV
OD
LVDS V
OD
Magnitude Change –50 – 50 mV
V
OS
LVDS Offset Output Voltage 1.125 1.25 1.375 mV
ΔV
OS
LVDS V
OS
Magnitude Change –25 – 25 mV
V
IH
Input High Voltage, SEL 0.7*V
DD
––V
V
IL
Input Low Voltage, SEL – – 0.3*V
DD
V
I
IH
Input High Current, SEL SEL
= V
DD
––10μA
I
IL
Input Low Current, SEL SEL
= V
SS
––20μA
C
IN
[5]
Input Capacitance, SEL – 4 – pF
V
VIN
VIN Input Voltage 0 – V
DD
V
I
VIN
VIN Input Current V
SS
≤ VIN
≤ V
DD
–10 – 60 μA
INL
VIN
[4, 5]
VIN to F
OUT
Integral Nonlinearity V
SS
≤ VIN
≤ V
DD
–1–%
[+] Feedback
CY2VC521-2
Document Number: 001-15599 Rev. *E Page 5 of 9
AC Electrical Characteristics
[4, 6]
Parameter Description Test Conditions Min Typ Max Unit
F
OUT
Output Frequency – 216 – MHz
PR Pull Range VIN = V
DD
to V
SS
, relative to frequency at
VIN = 1.65V, across operating temperature
and voltage range
±115 – – ppm
T
R
, T
F
[7]
Output Rise and Fall Times 20% and 80% of swing between steady state
levels
––0.5ns
T
J
Period Jitter, RMS – 7 – ps
T
Jitter(φ)
RMS Phase Jitter (Random) 216 MHz carrier, integrated 12 kHz–20 MHz – 1.3 – ps
PN Phase Noise 1 kHz offset from 216 MHz carrier – –95 – dBc/Hz
10 kHz offset from 216 MHz carrier – –120 – dBc/Hz
100 kHz offset from 216 MHz carrier – –127 – dBc/Hz
1 MHz offset from 216 MHz carrier – –123 – dBc/Hz
10 MHz offset from 216 MHz carrier – –130 – dBc/Hz
T
DC
[8]
Duty Cycle Measured at zero crossing point 45 50 55 %
T
LOCK
Start-up Time Time for CLK to reach valid frequency
measured from the time V
DD
= V
DD
(min.)
––5ms
Notes
6. Outputs are terminated with 50Ω between CLK and CLK#. Refer to Figure 2 on page 3.
7. Refer to Figure 6 on page 6.
8. Refer to Figure 7 on page 6.
[+] Feedback
CY2VC521-2
Document Number: 001-15599 Rev. *E Page 6 of 9
Parameter Measurements
Figure 4. Output Voltage Swing
Figure 5. Output Offset Voltage
Figure 6. Output Rise and Fall Time
Figure 7. Output Duty Cycle/Pulse Width/Period
CLK
CLK#
V
OD2
V
OD1
ΔV
OD
= V
OD1
- V
OD2
CLK
25Ω
CLK#
25Ω
V
OS
20%
80%
T
R
CLK
20%
80%
CLK#
T
F
CLK
T
PW
T
PERIOD
T
DC
=
T
PW
T
PERIOD
CLK#
[+] Feedback
P1-P3P4-P6P7-P9

CY2VC521ZXC-2T

Mfr. #:
Buy CY2VC521ZXC-2T
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK GEN PROGR 16TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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