GTL2005PW/G-T

1. General description

The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a

GTL/GTL+ bus.

The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling

receiver or as a TTL-to-GTL interface.

The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V

CMOS outputs.

The GTL2005 V

ref

I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O

I Live insertion/extraction permitted

I Latch-up protection exceeds 500 mA per JESD78

I ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per

JESD22-A115, and 1000 V CDM per JESD22-CC101

I Package offered: TSSOP14

GTL2005

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched

translator

Rev. 06 — 6 September 2007 Product data sheet

3. Quick reference data

Symbol Parameter Conditions Min Typ

C

=3.0Vor0V

- 2.3 3.5 pF

C

= 3.0 V or 0 V

- 6.0 7.0 pF

GTL; V

ref

= 0.8 V

t

PLH

t

PHL

- 4.4 5.9 ns

Table 2. Ordering information

−

Type number Topside

mark

5. Functional diagram

B0

B1

B2

B3

A0

A1

A2

A3

VREF DIR

DIR V

A0 B0

A1 B1

VREF GND

A2 B2

A3 B3