7
PS8326C 10/27/06
PI74VCX16373
16-Bit Transparent D-Type Latch
with 3-State Outputs
Test Circuits and Switching Waveforms
Parameter Measurement Information (VDD = 1.8V - 3.6V)
Setup, Hold, and Release Timing
Pulse Width
Switch Position
Propagaton Delay
Enable Disable Timing
Data
Input
t
H
V
DD
t
SU
0V
Timing
Input
V
DD
V
DD/2
V
DD/2
Low-High-Low
Pulse
t
W
High-Low-High
Pulse
DD
0V
V
DD
V
DD/2
V
DD/2
Input
Opposite Phase
Input Transition
tPLH
tPHL
tPLHtPHL
DD
0V
V
DD
VOL
VDD
Output
V
DD/2
VDD/2
VDD/2
Output
Control
(Active LOW)
Output
Waveform 2
S1 at GND
t
PZL
t
PLZ
DD
0V
V
DD
V
OL
0V
Output
Waveform 1
S1 at 2xV
DD
(see Note B)
+0.15V
-0.15V
V
OH
V
DD
t
PHZ
t
PZH
V
DD/2
V
DD/2
V
DD
/2
C
L
R
1
500Ω
30pF
From Output
Under Test
GND
DD
Open
(See Note A)
R
L
500Ω
tseT1S
t
DP
nepO
t
ZLP
t/
LZP
Vx2
DD
t
ZHP
t/
HZP
DNG
Notes:
A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that
the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is HIGH except when disabled by the output control.
• All input pulses are supplied by generators having the
following characteristics: P
RR
≤ 10 MHz, Z
O
= 50Ω, t
R
≤ 2ns, t
F
≤ 2ns,
measured from 10% to 90%, unless otherwise specified.
• The outputs are measured one at a time with one transition per
measurement.
