Data Sheet ADF4360-8
Rev. D | Page 3 of 24
SPECIFICATIONS
1
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter B Version Unit Test Conditions/Comments
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency 10/250 MHz min/max
For f < 10 MHz, use a dc-coupled CMOS-compatible square wave, slew
rate > 21 V/µs.
REF
IN
Input Sensitivity 0.7/AV
DD
V p-p min/max AC-coupled.
0 to AV
DD
V max CMOS-compatible.
REF
IN
Input Capacitance 5.0 pF max
REF
IN
Input Current ±60 µA max
PHASE DETECTOR
Phase Detector Frequency
2
8 MHz max
CHARGE PUMP
I
CP
Sink/Source
3
With R
SET
= 4.7 kΩ.
High Value 2.5 mA typ
0.312
mA typ
RSET Range 2.7/10 kΩ
I
CP
Three-State Leakage
Current
0.2 nA typ
Sink and Source Current
Matching
2 % typ 1.25 V V
CP
2.5 V.
I
CP
vs. V
CP
1.5 % typ 1.25 V ≤ V
CP
2.5 V.
I
CP
vs. Temperature 2 % typ V
CP
= 2.0 V.
V
INH
, Input High Voltage 1.5 V min
V
INL
, Input Low Voltage 0.6 V max
I
INH
/I
INL
, Input Current ±1 µA max
C
IN
, Input Capacitance 3.0 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage DV
DD
− 0.4 V min CMOS output chosen.
I
OH
, Output High Current 500 µA max
V
OL
, Output Low Voltage 0.4 V max I
OL
= 500 µA.
POWER SUPPLIES
AV
DD
3.0/3.6 V min/V max
DV
DD
AV
DD
VV
CO
AV
DD
AI
DD
4
5 mA typ
DI
DD
4
2.5 mA typ
IV
CO
4, 5
12.0 mA typ I
CORE
= 5 mA.
I
RFOUT
4
3.5 to 11.0 mA typ RF output stage is programmable.
4
7
µA typ
RF OUTPUT CHARACTERISTICS
5
Maximum VCO Output Frequency 400 MHz
I
CORE
= 5 mA. Depending on L. See the
Choosing the Correct Inductance Value section.
Minimum VCO Output Frequency 65 MHz
VCO Output Frequency 88/108 MHz min/max
L1, L2 = 270 nH. See the Choosing the Correct Inductance Value
section for other frequency values.
VCO Frequency Range 1.2 Ratio F
MAX
/F
MIN
VCO Sensitivity 2 MHz/V typ
L1, L2 = 270 nH. See the Choosing the Correct Inductance Value
section for other sensitivity values.
Lock Time
6
400 µs typ To within 10 Hz of final frequency.
Frequency Pushing (Open Loop) 0.24 MHz/V typ
ADF4360-8 Data Sheet
Rev. D | Page 4 of 24
Parameter B Version Unit Test Conditions/Comments
Frequency Pulling (Open Loop) 10 Hz typ Into 2.00 VSWR load.
Harmonic Content (Second) −16 dBc typ
Harmonic Content (Third) −21 dBc typ
Output Power
5, 7
−9/0 dBm typ Using tuned load, programmable in 3 dB steps; see Table 7.
−14/−9
dBm typ
Using 50 resistors to V
VCO
, programmable in 3 dB steps; see Table 7.
Output Power Variation ±3 dB typ
VCO Tuning Range 1.25/2.5 V min/max
VCO Phase Noise Performance
9
−120 dBc/Hz typ At 100 kHz offset from carrier.
−139 dBc/Hz typ At 800 kHz offset from carrier.
−140 dBc/Hz typ At 3 MHz offset from carrier.
−142 dBc/Hz typ At 10 MHz offset from carrier.
Synthesizer Phase Noise Floor
10
−160 dBc/Hz typ At 200 kHz PFD frequency.
−150
dBc/Hz typ
At 1 MHz PFD frequency.
−142 dBc/Hz typ At 8 MHz PFD frequency.
Phase Noise Figure of Merit
10
−215 dBc/Hz typ
In-Band Phase Noise
11, 12
−102 dBc/Hz typ At 1 kHz offset from carrier.
RMS Integrated Phase Error
13
0.09 Degrees typ 100 Hz to 100 kHz.
Frequency
12, 14
−75
dBc typ
Level of Unlocked Signal with
MTLD Enabled
−70 dBm typ
1
Operating temperature range is 40°C to +85°C.
2
Guaranteed by design. Sample tested to ensure compliance.
3
I
CP
is internally modified to maintain constant loop gain over the frequency range.
4
T
A
= 25°C; AV
DD
= DV
DD
= V
VCO
= 3.3 V.
5
Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.
6
Jumping from 88 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
For more detail on using tuned loads, see the Output Matching section.
8
Using 50 resistors to V
VCO
, into a 50 load.
9
The noise of the VCO is measured in open-loop conditions.
10
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). The
phase noise figure of merit subtracts 10 log (PFD frequency).
11
The phase noise is measured with the EV-ADF4360-8EB1Z evaluation board and the HP 8562E spectrum analyzer. The spectrum analyzer provides the REF
IN
for the
synthesizer; offset frequency = 1 kHz.
12
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; N = 1000; loop bandwidth = 10 kHz.
13
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; N = 120; loop bandwidth = 100 kHz.
14
The spurious signals are measured with the EV-ADF4360-8EB1Z evaluation board and the HP 8562E spectrum analyzer. The spectrum analyzer provides the REF
IN
for
the synthesizer; f
REFOUT
= 10 MHz at 0 dBm.
Data Sheet ADF4360-8
Rev. D | Page 5 of 24
TIMING CHARACTERISTICS
1
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Limit at T
MIN
to T
MAX
(B Version) Unit Test Conditions/Comments
t
1
20 ns min LE setup time
t
2
10 ns min DATA to CLOCK setup time
t
3
10 ns min DATA to CLOCK hold time
t
4
25 ns min CLOCK high duration
t
5
25 ns min CLOCK low duration
t
6
10 ns min CLOCK to LE setup time
t
7
20 ns min LE pulse width
1
Refer to the Power-Up section for the recommended power-up procedure for this device.
CLOC
K
DATA
LE
LE
DB23 (MSB) DB22 DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
04763-002
Figure 2. Timing Diagram

RB051MM-2YTR

Mfr. #:
Manufacturer:
Description:
Schottky Diodes & Rectifiers Schottky Barrier Diodes
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union