AD7792/AD7793
Rev. B | Page 22 of 32
Single Conversion Mode
In single conversion mode, the AD7792/AD7793 are placed in
shutdown mode between conversions. When a single conver-
sion is initiated by setting MD2, MD1, MD0 to 0, 0, 1 in the
mode register, the AD7792/AD7793 power up, perform a single
conversion, and then return to shutdown mode. The on-chip
oscillator requires 1 ms to power up. A conversion requires a
time period of 2 × t
ADC
. DOUT/
RDY
goes low to indicate the
completion of a conversion. When the data-word has been read
from the data register, DOUT/
RDY
goes high. If
CS
is low,
DOUT/
RDY
remains high until another conversion is initiated
and completed. The data register can be read several times, if
required, even when DOUT/
RDY
has gone high.
Continuous Conversion Mode
This is the default power-up mode. The AD7792/AD7793
continuously converts, the
RDY
pin in the status register going
low each time a conversion is completed. If
CS
is low, the
DOUT/
RDY
line also goes low when a conversion is complete.
To read a conversion, the user writes to the communications
register indicating that the next operation is a read of the data
register. The digital conversion is placed on the DOUT/
RDY
pin as soon as SCLK pulses are applied to the ADC.
DOUT/
RDY
returns high when the conversion is read. The
user can read this register additional times, if required.
However, the user must ensure that the data register is not being
accessed at the completion of the next conversion, otherwise the
new conversion word is lost.
0x58
04855-015
DIN
0x08 0x200A
DATA
SCLK
DOUT/RDY
CS
Figure 17. Single Conversion
0
4855-016
DIN
SCLK
DOUT/RDY
CS
0x58 0x58
DATA DATA
Figure 18. Continuous Conversion
AD7792/AD7793
Rev. B | Page 23 of 32
Continuous Read
Rather than write to the communications register each time a
conversion is complete to access the data, the AD7792/AD7793
can be configured so that the conversions are placed on the
DOUT/
RDY
line automatically. By writing 01011100 to the
communications register, the user needs only to apply the
appropriate number of SCLK cycles to the ADC, and the 16/24-
bit word is automatically placed on the DOUT/
RDY
line when a
conversion is complete. The ADC should be configured for
continuous conversion mode.
When DOUT/
RDY
goes low to indicate the end of a conver-
sion, sufficient SCLK cycles must be applied to the ADC, and
the data conversion is placed on the DOUT/
RDY
line. When
the conversion is read, DOUT/
RDY
returns high until the next
conversion is available. In this mode, the data can be read only
once. In addition, the user must ensure that the data-word is
read before the next conversion is complete. If the user has not
read the conversion before the completion of the next
conversion, or if insufficient serial clocks are applied to the
AD7792/AD7793 to read the word, the serial output register is
reset when the next conversion is completed, and the new
conversion is placed in the output serial register.
To exit the continuous read mode, the instruction 01011000
must be written to the communications register while the
DOUT/
RDY
pin is low. While in the continuous read mode, the
ADC monitors activity on the DIN line so that it can receive the
instruction to exit the continuous read mode. Additionally, a
reset occurs if 32 consecutive 1s are seen on DIN. Therefore,
DIN should be held low in continuous read mode until an
instruction is written to the device.
04855-017
DIN
SCLK
DOUT/RDY
CS
0x5C
DATA DATA DATA
Figure 19. Continuous Read
AD7792/AD7793
Rev. B | Page 24 of 32
CIRCUIT DESCRIPTION
ANALOG INPUT CHANNEL
The AD7792/AD7793 have three differential analog input
channels. These are connected to the on-chip buffer amplifier
when the device is operated in buffered mode and directly to
the modulator when the device is operated in unbuffered mode.
In buffered mode (the BUF bit in the mode register is set to 1),
the input channel feeds into a high impedance input stage of the
buffer amplifier. Therefore, the input can tolerate significant
source impedances and is tailored for direct connection to
external resistive-type sensors, such as strain gauges or
resistance temperature detectors (RTDs).
When BUF = 0, the part is operated in unbuffered mode.
This results in a higher analog input current. Note that this
unbuffered input path provides a dynamic load to the driving
source. Therefore, resistor/capacitor combinations on the input
pins can cause gain errors, depending on the output impedance
of the source that is driving the ADC input.
Table 19 shows the
allowable external resistance/capacitance values for unbuffered
mode such that no gain error at the 20-bit level is introduced.
Table 19. External R-C Combination for No 20-Bit Gain Error
C (pF) R (Ω)
50 9 k
100 6 k
500 1.5 k
1000 900
5000 200
The AD7792/AD7793 can be operated in unbuffered mode only
when the gain equals 1 or 2. At higher gains, the buffer is auto-
matically enabled. The absolute input voltage range in buffered
mode is restricted to a range between GND + 100 mV and
AV
DD
– 100 mV. When the gain is set to 4 or higher, the in-amp
is enabled. The absolute input voltage range when the in-amp is
active is restricted to a range between GND + 300 mV and
AV
DD
− 1.1 V. Take care in setting up the common-mode
voltage so that these limits are not exceeded to avoid
degradation in linearity and noise performance.
The absolute input voltage in unbuffered mode includes the
range between GND – 30 mV and AV
DD
+ 30 mV as a result of
being unbuffered. The negative absolute input voltage limit does
allow the possibility of monitoring small true bipolar signals
with respect to GND.
INSTRUMENTATION AMPLIFIER
Amplifying the analog input signal by a gain of 1 or 2 is
performed digitally within the AD7792/AD7793. However,
when the gain equals 4 or higher, the output from the buffer is
applied to the input of the on-chip instrumentation amplifier.
This low noise in-amp means that signals of small amplitude
can be gained within the AD7792/AD7793 while still
maintaining excellent noise performance.
For example, when the gain is set to 64, the rms noise is 40 nV
typically, which is equivalent to 21 bits effective resolution or
18.5 bits peak-to-peak resolution.
The AD7792/AD7793 can be programmed to have a gain of 1,
2, 4, 8, 16, 32, 64, and 128 using Bit G2 to Bit G0 in the configu-
ration register. Therefore, with an external 2.5 V reference, the
unipolar ranges are from 0 mV to 20 mV to 0 V to 2.5 V while
the bipolar ranges are from ±20 mV to ±2.5 V. When the
in-amp is active (gain ≥ 4), the common-mode voltage (AIN(+)
+ AIN(–))/2 must be greater than or equal to 0.5 V.
If the AD7792/AD7793 are operated with an external reference
that has a value equal to AV
DD
, the analog input signal must be
limited to 90% of V
REF
/gain when the in-amp is active, for
correct operation.
BIPOLAR/UNIPOLAR CONFIGURATION
The analog input to the AD7792/AD7793 can accept either
unipolar or bipolar input voltage ranges. A bipolar input range
does not imply that the part can tolerate negative voltages with
respect to system GND. Unipolar and bipolar signals on the
AIN(+) input are referenced to the voltage on the AIN(–) input.
For example, if AIN(−) is 2.5 V, and the ADC is configured for
unipolar mode and a gain of 1, the input voltage range on the
AIN(+) pin is 2.5 V to 5 V.
If the ADC is configured for bipolar mode, the analog input
range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar
option is chosen by programming the U/
B
bit in the configura-
tion register.
DATA OUTPUT CODING
When the ADC is configured for unipolar operation, the output
code is natural (straight) binary with a zero differential input
voltage resulting in a code of 00...00, a midscale voltage
resulting in a code of 100...000, and a full-scale input voltage
resulting in a code of 111...111. The output code for any analog
input voltage can be represented as
Code = (2
N
× AIN × GAIN)/V
REF
When the ADC is configured for bipolar operation, the output
code is offset binary with a negative full-scale voltage resulting
in a code of 000...000, a zero differential input voltage resulting
in a code of 100...000, and a positive full-scale input voltage
resulting in a code of 111...111. The output code for any analog
input voltage can be represented as
Code = 2
N – 1
× [(AIN × GAIN /V
REF
) + 1]
where AIN is the analog input voltage, GAIN is the in-amp
setting (1 to 128), and N = 16 for the AD7792 and N = 24 for
the AD7793.

AD7793BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3Ch Lo Noise Lo Pwr 24B w/ On-Chip Ref
Lifecycle:
New from this manufacturer.
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