AD7793BRUZ Datasheet AD7793BRUZ-REEL, AD7793BRUZ, AD7792BRUZ-REEL | P25-P27

AD7792/AD7793

Rev. B | Page 25 of 32

BURNOUT CURRENTS

The AD7792/AD7793 contain two 100 nA constant current

generators, one sourcing current from AV

to AIN(+) and one

sinking current from AIN(–) to GND. The currents are

switched to the selected analog input pair. Both currents are

either on or off, depending on the burnout current enable (BO)

bit in the configuration register. These currents can be used to

verify that an external transducer is still operational before

attempting to take measurements on that channel. Once the

burnout currents are turned on, they flow in the external

transducer circuit, and a measurement of the input voltage on

the analog input channel can be taken. If the resultant voltage

measured is full scale, the user needs to verify why this is the

case. A full-scale reading could mean that the front-end sensor

is open circuit. It could also mean that the front-end sensor is

overloaded and is justified in outputting full scale, or the

reference may be absent, thus clamping the data to all 1s.

When reading all 1s from the output, the user needs to check

these three cases before making a judgment. If the voltage

measured is 0 V, it may indicate that the transducer has short

circuited. For normal operation, these burnout currents are

turned off by writing a 0 to the BO bit in the configuration

input voltage range specifications with buffers on.

EXCITATION CURRENTS

The AD7792/AD7793 also contain two matched, software

configurable, constant current sources that can be programmed

to equal 10 μA, 210 μA, or 1 mA. Both source currents from the

are directed to either the IOUT1 or IOUT2 pin of the

device. These current sources are controlled via bits in the IO

direct the current sources to IOUT1 or IOUT2, and select the

value of the current. These current sources can be used to excite

external resistive bridge or RTD sensors.

BIAS VOLTAGE GENERATOR

A bias voltage generator is included on the AD7792/AD7793.

This biases the negative terminal of the selected input channel

to AV

/2. It is useful in thermocouple applications, because the

voltage generated by the thermocouple must be biased about

some dc voltage if the gain is greater than 2. This is necessary

because the instrumentation amplifier requires headroom to

ensure that signals close to GND or AV

are converted

accurately.

The bias voltage generator is controlled using the VBIAS1 and

VBIAS0 bits in conjunction with the boost bit in the configura-

tion register. The power-up time of the bias voltage generator is

dependent on the load capacitance. To accommodate higher

load capacitances, the AD7792/AD7793 have a boost bit. When

this bit is set to 1, the current consumed by the bias voltage

generator increases, so that the power-up time is considerably

reduced.

Figure 10 shows the power-up time when boost equals

0 and 1 for different load capacitances.

The current consumption of the AD7792/AD7793 increases by

40 μA when the bias voltage generator is enabled, and boost

equals 0. With the boost function enabled, the current

consumption increases by 250 μA.

REFERENCE

The AD7792/AD7793 have an embedded 1.17 V reference that

can be used to supply the ADC, or an external reference can be

applied. The embedded reference is a low noise, low drift

reference, the drift being 4 ppm/°C typically. For external

references, the ADC has a fully differential input capability for

the channel. The reference source for the AD7792/AD7793 is

selected using the REFSEL bit in the configuration register.

When the internal reference is selected, it is internally con-

nected to the modulator. It is not available on the REFIN pins.

The common-mode range for these differential inputs is from

GND to AV

. The reference input is unbuffered; therefore,

excessive R-C source impedances introduce gain errors. The

reference voltage REFIN (REFIN(+) − REFIN(−)) is 2.5 V

nominal, but the AD7792/AD7793 are functional with reference

voltages from 0.1 V to AV

. In applications where the exci-

tation (voltage or current) for the transducer on the analog

input also drives the reference voltage for the part, the effect

of the low frequency noise in the excitation source is removed

because the application is ratiometric. If the AD7792/AD7793

are used in a nonratiometric application, a low noise reference

should be used.

Recommended 2.5 V reference voltage sources for the AD7792/

AD7793 include the ADR381 and ADR391, which are low noise,

low power references. Also note that the reference inputs

provide a high impedance, dynamic load. Because the input

impedance of each reference input is dynamic, resistor/capacitor

combinations on these inputs can cause dc gain errors, depending

on the output impedance of the source that is driving the

reference inputs.

Reference voltage sources like those recommended above (such

as ADR391) typically have low output impedances and are,

therefore, tolerant to having decoupling capacitors on REFIN(+)

without introducing gain errors in the system. Deriving the

reference input voltage across an external resistor means that

the reference input sees a significant external source impedance.

External decoupling on the REFIN pins is not recommended in

this type of circuit configuration.

RESET

The circuitry and serial interface of the AD7792/AD7793 can

be reset by writing 32 consecutive 1s to the device. This resets

the logic, the digital filter, and the analog modulator while all

on-chip registers are reset to their default values. A reset is

automatically performed on power-up. When a reset is initiated,

the user must allow a period of 500 μs before accessing any of

the on-chip registers. A reset is useful if the serial interface

becomes asynchronous due to noise on the SCLK line.

AD7792/AD7793

Rev. B | Page 26 of 32

MONITOR

Along with converting external voltages, the ADC can be used

to monitor the voltage on the AV

pin. When Bit CH2 to

Bit CH0 equal 1, the voltage on the AV

pin is internally

attenuated by 6, and the resultant voltage is applied to the ∑-Δ

modulator using an internal 1.17 V reference for analog-to-

digital conversion. This is useful, because variations in the

power supply voltage can be monitored.

CALIBRATION

The AD7792/AD7793 provide four calibration modes that can

be programmed via the mode bits in the mode register. These

are internal zero-scale calibration, internal full-scale calibration,

system zero-scale calibration, and system full-scale calibration,

which effectively reduces the offset error and full-scale error to

the order of the noise. After each conversion, the ADC con-

version result is scaled using the ADC calibration registers

before being written to the data register. The offset calibration

coefficient is subtracted from the result prior to multiplication

by the full-scale coefficient.

To start a calibration, write the relevant value to the MD2 to

MD0 bits in the mode register. After the calibration is complete,

the contents of the corresponding calibration registers are

updated, the

RDY

bit in the status register is set, the DOUT/

RDY

pin goes low (if

is low), and the AD7792/AD7793

revert to idle mode.

During an internal zero-scale or full-scale calibration, the

respective zero input and full-scale input are automatically

connected internally to the ADC input pins. A system

calibration, however, expects the system zero-scale and system

full-scale voltages to be applied to the ADC pins before the

calibration mode is initiated. In this way, external ADC errors

are removed.

From an operational point of view, a calibration should be

treated like another ADC conversion. A zero-scale calibration

(if required) should always be performed before a full-scale

calibration. System software should monitor the

RDY

bit in

the status register or the DOUT/

RDY

pin to determine the

end of calibration via a polling sequence or an interrupt-driven

routine.

Both an internal offset calibration and a system offset

calibration take two conversion cycles. An internal offset

calibration is not needed, as the ADC itself removes the offset

continuously.

To perform an internal full-scale calibration, a full-scale input

voltage is automatically connected to the selected analog input

for this calibration. When the gain equals 1, a calibration takes

2 conversion cycles to complete. For higher gains, 4 conversion

cycles are required to perform the full-scale calibration.

DOUT/

RDY

goes high when the calibration is initiated and

returns low when the calibration is complete.

The ADC is placed in idle mode following a calibration. The

measured full-scale coefficient is placed in the full-scale register

of the selected channel. Internal full-scale calibrations cannot be

performed when the gain equals 128. With this gain setting, a

system full-scale calibration can be performed. A full-scale

calibration is required each time the gain of a channel is

changed to minimize the full-scale error.

An internal full-scale calibration can be performed at specified

update rates only. For gains of 1, 2, and 4, an internal full-scale

calibration can be performed at any update rate. However, for

higher gains, internal full-scale calibrations can be performed

when the update rate is less than or equal to 16.7 Hz, 33.2 Hz,

and 50 Hz only. However, the full-scale error does not vary with

update rate, so a calibration at one update rate is valid for all

update rates (assuming the gain or reference source is not

changed).

A system full-scale calibration takes 2 conversion cycles to

complete, irrespective of the gain setting. A system full-scale

calibration can be performed at all gains and all update rates. If

system offset calibrations are being performed along with

system full-scale calibrations, the offset calibration should be

performed before the system full-scale calibration is initiated.

GROUNDING AND LAYOUT

Because the analog inputs and reference inputs of the ADC are

differential, most of the voltages in the analog modulator are

common-mode voltages. The excellent common-mode reject-

ion of the part removes common-mode noise on these inputs.

The digital filter provides rejection of broadband noise on the

power supply, except at integer multiples of the modulator

sampling frequency. The digital filter also removes noise from

the analog and reference inputs, provided that these noise

sources do not saturate the analog modulator. As a result, the

AD7792/AD7793 are more immune to noise interference than a

conventional high resolution converter. However, because the

resolution of the AD7792/AD7793 is so high, and the noise

levels from the AD7792/AD7793 are so low, care must be taken

with regard to grounding and layout.

The printed circuit board that houses the AD7792/AD7793

should be designed such that the analog and digital sections are

separated and confined to certain areas of the board. A mini-

mum etch technique is generally best for ground planes because

it provides the best shielding.

It is recommended that the GND pins of the AD7792/AD7793

be tied to the AGND plane of the system. In any layout, it is

important to keep in mind the flow of currents in the system,

ensuring that the return paths for all currents are as close as

possible to the paths the currents took to reach their destinations.

Avoid forcing digital currents to flow through the AGND

sections of the layout.

AD7792/AD7793

Rev. B | Page 27 of 32

The ground planes of the AD7792/AD7793 should be allowed

to run under the AD7792/AD7793 to prevent noise coupling.

The power supply lines to the AD7792/AD7793 should use as

wide a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals such as clocks should be shielded with digital

ground to avoid radiating noise to other sections of the board,

and clock signals should never be run near the analog inputs.

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough through the

board. A microstrip technique is by far the best, but it is not

always possible with a double-sided board. In this technique,

the component side of the board is dedicated to ground planes,

and signals are placed on the solder side.

Good decoupling is important when using high resolution

ADCs. AV

should be decoupled with 10 μF tantalum in

parallel with 0.1 μF capacitors to GND. DV

should be

decoupled with 10 μF tantalum in parallel with 0.1 μF

capacitors to the system’s DGND plane, with the system’s

AGND to DGND connection being close to the

AD7792/AD7793.

To achieve the best from these decoupling components, they

should be placed as close as possible to the device, ideally right

up against the device. All logic chips should be decoupled with

0.1 μF ceramic capacitors to DGND.

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Analog to Digital Converters - ADC 3Ch Lo Noise Lo Pwr 24B w/ On-Chip Ref

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