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PI2EQX4401DZFEX

P1-P3P4-P6P7-P8
1
PS8872H 09/26/08
Features
• One high-speed PCI-Express lane
• Adjustable Transmiter De-Emphasis & Amplitude
• Adjustable Receiver Equalization
• One Spread Spectrum Reference Clock Buffer Output
• Input Signal Level Detect and Output Squelch
• 100Ω Differential CML I/O’s
• Low Power (100mW per Channel)
• Stand-by Mode – Power Down State
• V
DD
Operating Range: 1.8V ±0.1V
• Packaging (Pb-free & Green):
— 36-pad TQFN (ZF36)
Description
Pericom Semiconductor’s PI2EQX4401D is a low power,
PCI-Express compliant signal re-driver. The device provides
programmable equalization, amplifi cation, and de-emphasis
by using 4 select bits, SEL[0:3], to optimize performance
over a variety of physical mediums by reducing Inter-symbol
interference. PI2EQX4401D supports two 100Ω Differential
CML data I/O’s between the Protocol ASIC to a switch fabric,
across a backplane, or extends the signals across other distant
data pathways on the user’s platform.
The integrated equalization circuitry provides fl exibility with
signal integrity of the PCI-express signal before the re-driver.
Whereas the integrated de-emphasis circuitry provides fl exibility
with signal integrity of the PCI-express signal after the Re-
Driver.
A low-level input signal detection and output squelch function
is provided for both channels. Each channel operates fully
independantly. When a channel is enabled (EN_x=1) and
operating, that channel's input signal level (on xl+/-) determines
whether the output is enabled. If the input level of the channel
falls below the active threshold level (Vth-) then the output driver
switches off, and the pin is pulled to VDD via a high impedance
resistor.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX4401D also provides power management Stand-by
mode operated by a Bus Enable pin. A differential clock buffer
is provided for test and other system requirements. This clock
function is not used by the data channels.
PI2EQX4401D
2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer
with Clock Buffer & Signal Detect Feature
08-0241
2
PS8872H 09/26/08
PI2EQX4401D
2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer
with Clock Buffer & Signal Defect FeaTure
Block Diagram
Pin Description
V
DD
AI+
AI-
GND
AV
DD
V
DD
B
0
+
B
0
-
GND
V
DD
V
DD
A
0
+
A
0
-
GND
AGND
V
DD
BI+
BI-
GND
IREF
SIG_A
SIG_B
SEL0_A
SEL1_A
SEL2_A
SEL3_A
EN_A
EN_B
OUT-
OUT+
SEL3_B
SEL2_B
SEL1_B
SEL0_B
CLK
IN-
CLK
IN+
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
11 12 13
14
15 16 17 18
36 35 34
33
32 31 30 29
GND
xl+
CML
LVCMOS
SIG_x
xO+
xO-
CML
Limiting
Amp
Equalizer
SEL[0:1]
CLKIN-
CLKIN+
OUT0-
OUT0+
SEL[2]_x
SEL
Buffer
CLK
IREF
xl+
08-0241
3
PS8872H 09/26/08
PI2EQX4401D
2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer
with Clock Buffer & Signal Defect Feature
Pin Description
Pin # Pin Name I/O Description
1, 6, 10, 23, 28 V
DD
PWR 1.8V Supply Voltage
2 AI+ I
Positive CML Input Channel A with internal 50Ω pull down during normal
operation (EN_A=1). When EN_A=0, this pin is high-impedance.
3 AI- I
Negative CML Input Channel A with internal 50Ω pull down during normal
operation (EN_A=1). When EN_A=0, this pin is high-impedance.
4, 9, 20, 25 GND PWR Supply Ground
22 BI+ I
Positive CML Input Channel B with internal 50Ω pull down during normal
operation (EN_B=1). When EN_B=0, this pin is high-impedance.
21 BI- I
Negative CML Input Channel B with internal 50Ω pull down during normal
operation (EN_B=1). When EN_B=0, this pin is high-impedance.
34, 33 SEL[0:1]_A I
Selection pins for equalizer (see Amplifi er Confi guration Table)
w/ 50KΩ internal pull up
13, 14 SEL[0:1]_B I
32 SEL[2]_A I
Selection pins for amplifi er (see Amplifi er Confi guration Table)
w/ 50KΩ internal pull up
15 SEL[2]_B I
31 SEL[3]_A I
Selection pins for De-Emphasis (See De-Emphasis Confi guration Table)
w/ 50KΩ internal pull up
16 SEL[3]_B I
27 AO+ O
Positive CML Output Channel A internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
26 AO- O
Negative CML Output Channel A with internal 50Ω pull up during normal
operation and 2KΩ pull up otherwise.
7 BO+ O
Positive CML Output Channel B with internal 50Ω pull up during normal
operation and 2KΩ pull up otherwise.
8 BO- O
Negative CMLOutput Channel B with internal 50Ω pull up during normal
operation and 2KΩ pull up otherwise.
30, 29 EN_[A,B] I
EN_[A:B] is the enable pin. A LVCMOS high provides normal operation. A
LVCMOS low selects a low power down mode.
12 CLKIN- I
Differential Input Reference Clock. If clock buffer is not used, then both
CLKIN+, CLKIN- should be pulled high to VDD.
11 CLKIN+ I
17, 18 OUT+, OUT- O Differential Reference Clock Output
5 AVDD PWR 1.8V Analog supply voltage
24 AGND PWR Analog ground
19 IREF O
External 475Ω resistor connection to set the differential output current. If the
clock buffer is not used, then IREF should be unconnected (open).
36, 35 SIG_A, SIG_B O
SIG Detector output for channel A-B. Provides a LVCMOS high output when
an input signal greater than the threshold is detected
08-0241
P1-P3P4-P6P7-P8

PI2EQX4401DZFEX

Mfr. #:
Buy PI2EQX4401DZFEX
Manufacturer:
Diodes Incorporated
Description:
PCI Interface IC 2.5Gbps PCI-Express ReDriver
Lifecycle:
New from this manufacturer.
Delivery:
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