7
PS8872H 09/26/08
PI2EQX4401D
2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer
with Clock Buffer & Signal Defect Feature
AC Switching Characteristics for Clock Buffer (V
DD
= 1.8 ±0.1V, AV
DD
= 1.8 ±0.1V)
Symbol Parameters Min Max. Units Notes
T
rise
/ T
fall
Rise and Fall Time (measured between 0.175V to 0.525V) 125 525
ps
1
T
rise
/
T
fall
Rise and Fall Time Variation 75 1
V
HIGH
Voltage High including overshoot 660 900
mV
1
V
LOW
Voltage Low including undershoot -200 1
V
CROSS
Absolute crossing point voltages 200 550 1
V
CROSS
Total Variation of Vcross over all edges 250 1
T
DC
Duty Cycle (input duty cycle = 50%) 45 55 % 2
Notes:
1. Measurement taken from Single Ended waveform.
2. Measurement taken from Differential waveform.
3. Test confi guration is R
S
= 33.2Ω, Rp = 49.9Ω, and 2pF.
Confi guration Test Load Board Termination
Figure 2. Confi guration test load board termination
Note:
1. TLA and TLB are 3” transmission lines.
Rs
33Ω
5%
Rs
33Ω
5%
Rp
49.9Ω
1%
475Ω
1%
Rp
49.9Ω
1%
2pF
5%
2pF
5%
Clock#
Clock
TLA
TLB
CLKBUF
