MAX2067
50MHz to 1000MHz High-Linearity,
Serial/Analog-Controlled VGA
20 ______________________________________________________________________________________
Table 4. Typical Application Circuit Component Values (HC Mode)
DESIGNATION VALUE SIZE VENDOR DESCRIPTION
C1, C2, C7, C12 10nF 0402 Murata Mfg. Co., Ltd. X7R
C3, C4, C6, C8, C9 1000pF 0402 Murata Mfg. Co., Ltd. C0G ceramic capacitors
C10, C11 150pF 0402 Murata Mfg. Co., Ltd. C0G ceramic capacitors
L1 470nH 1008 Coilcraft, Inc. 1008CS-471XJLC
R1, R1A 10Ω 0402 Panasonic Corp. 1%
R2 (+3.3V applications only) 1kΩ 0402 Panasonic Corp. 1%
R3 (+3.3V applications only) 2kΩ 0402 Panasonic Corp. 1%
R4 (+5V applications and
using internal DAC only)
47kΩ 0402 Panasonic Corp. 1%
U1 —
40-pin thin QFN-EP
(6mm x 6mm)
Maxim Integrated
Products, Inc.
MAX2067ETL+
External Bias
Bias currents for the driver amplifier are set and opti-
mized through external resistors. Resistors R1 and R1A
connected to RSET (pin 18) set the bias current for the
amplifier. The external biasing resistor values can be
increased for reduced current operation at the expense
of performance. See Tables 4 and 5 for details.
Pin-Compatibility Considerations
The MAX2067 is a simplified version of the MAX2065
analog/digital VGA. The MAX2067 does not contain a
digital attenuator and parallel inputs D0–D4. The asso-
ciated input/output pins are internally connected to
ground (Table 3). Ground the unused input/output pins
to optimize isolation.
(
See the
Typical Application
Circuit.)
+5V and +3.3V Supply Voltage
The MAX2067 features an optional +3.3V supply voltage
operation with slightly reduced linearity performance.
Layout Considerations
The pin configuration of the MAX2067 has been opti-
mized to facilitate a very compact physical layout of the
device and its associated discrete components.
The exposed paddle (EP) of the MAX2067’s 40-pin thin
QFN-EP package provides a low thermal-resistance
path to the die. It is important that the PCB on which the
MAX2067 is mounted be designed to conduct heat
from the EP. In addition, provide the EP with a low-
inductance path to electrical ground. The EP must be
soldered to a ground plane on the PCB, either directly
or through an array of plated via holes.
Table 3. MAX2065/MAX2067 Pin
Comparison
PIN MAX2065 MAX2067
8 SER/PAR GND
9 STATE_A GND
10 STATE_B GND
11 D4 GND
12 D3 GND
13 D2 GND
14 D1 GND
15 D0 GND
23 ATTEN2_OUT GND
29 ATTEN2_IN GND
