CS5510-ASZ Datasheet CS5511-ASZ, CS5513-BSZ, CS5510-ASZ | P19-P21

CS5510/11/12/13

DS337F4 19

valid conversion due to the modified Sinc

filter

characteristics.

2.5.5 Multiplexed Applications

The settling performance of the CS5510/11/12/13

in multiplexed applications is determined by the

Sinc

filter. To settle, a step input requires 4 full

conversion cycles after the analog input has

switched. In this case, the throughput is reduced

by a factor of four as the first three conversions af-

ter the step is applied will not be fully settled.

If the application does not require the maximum

throughput possible from the ADC, the multiplexer

can be switched at any time. In this case, the sys-

tem must wait for at least five conversion cycles for

a fully-settled result from the ADC.

If maximum throughput is required in a multiplexed

application, the multiplexer must be switched at the

correct time during the data collection process. For

maximum throughput with the CS5510/12, switch-

ing of a multiplexer should occur 595 SCLK cycles

after SDO falls. For maximum throughput with the

CS5511/13, switching of a multiplexer should oc-

cur on the rising edge of SDO during a conversion

in which the data word is not read. The conversion

data that is immediately available when SDO falls

again is valid, and represents the analog input from

the previous multiplexer setting. The next three

conversions from the part will be unsettled values,

and the fourth conversion will represent a fully-set-

tled result from the new multiplexer setting. The

multiplexer should be switched again at the appro-

-140

-120

-100

-80

-60

-40

-20

02040

80 100 120

Frequency (Hz)

Magnitude (dB)

47 Hz

63 Hz

CS5510/12

SCLK = 32.768 kHz

Figure 20. Digital Filter Response.

Frequency

(Hz)

Rejection

(dB)

Frequency

(Hz)

Rejection

(dB)

Frequency

(Hz)

Rejection

(dB)

Frequency

(Hz)

Rejection

(dB)

38 37 47 84 56 91 65 73

39 39 48 92 57 109 66 69

40 42 49 88 58 94 67 66

41 46 50 92 59 89 68 64

42 49 51 105 60 88 69 63

43 54 52 89 61 92 70 61

44 58 53 86 62 104 71 60

45 64 54 85 63 84 - -

46 72 55 87 64 77 - -

Table 4. Digital Filter Response at 32.768 kHz.

CS5510/11/12/13

20 DS337F4

priate time during the third conversion cycle to en-

sure the maximum possible throughput.

2.6 Digital Off-chip System

Calibration

The CS5510/11/12/13 exhibit excellent linearity

with low offset and gain drift, without the need for

calibration. If precision voltage measurements are

required by the system, however, software-based

offset and gain calibration can be performed by the

system.

To perform a software offset calibration, the “zero-

point” of the system should be established by ap-

plying an input to the system equal to zero. Then,

the user can obtain a conversion and store it in

memory as the system’s zero point (ZP). This num-

ber can then be used as the zero point for any sub-

sequent conversion words. In the 20-bit devices

(CS5512 and CS5513), multiple conversions can

be averaged to arrive at a more accurate offset val-

ue. In the 16-bit devices (CS5510 and CS5511),

averaging may not be meaningful, because the

noise will be below the size of one LSB when using

nominal voltages for VREF (2.5 V).

A software gain calibration can be performed by

bringing the system to a known calibration Voltage

value (Vcal) and acquiring a conversion (note that

Vcal should be low enough to compensate for the

possible gain error of the ADC). Multiple conver-

sions can be averaged at this point to improve the

accuracy of the calibration. The code obtained

from this conversion is the real value (Cr) of the

calibration Voltage input, and will differ from the

ideal value. The ideal value for this conversion (Ci)

will be equivalent to: 0x7FFF*Vcal/(0.80*Vref) for

the CS5510/11, and 0x7FFFF*Vcal/(0.80*Vref) for

the CS5512/13. The gain error (GE) is equal to: (Cr

- ZP)/Ci. To correct for both offset and gain error in

subsequent conversions, subtract the offset error,

and then divide by the gain error.

2.7 Power Consumption, Sleep and

Reset

The CS5510/11/12/13 accommodates two power

modes: normal and sleep. The normal mode is the

default mode and is entered after power is estab-

lished to the ADC. In normal mode, the ADCs typ-

ically consumes 2.5 mW. Sleep is entered when

the user leaves SCLK high for at least 200 μs. The

ADCs are guaranteed to be in sleep after SCLK is

high (logic 1) for 2 ms. The sleep mode reduces

the consumed power to less than 10 μW when CS

is high (logic 1). If CS is low (logic 0) at this time,

the SDO drive logic will still be active, and the con-

sumed sleep power will be greater. To exit sleep

and return to normal mode, the user must return

SCLK low for at least 10 μs. After a sleep is exited,

the ADCs reset all their internal logic, including

their digital filters, and begin performing conver-

sions. Since the filters are reset, the first three con-

version after returning to normal mode will not be

fully settled.

2.8 PCB Layout

The CS5510/11/12/13 should be placed entirely

over the analog ground. Place the analog-digital

plane split immediately adjacent to the digital pins

of the chip.

CS5510/11/12/13

DS337F4 21

3. PIN DESCRIPTIONS

Control Pins and Serial Data I/O

CS - Chip Select, Pin 4

CS is a dual function pin, which determines the state of SDO, as well as the digital logic-low output

level. When CS

is low, SDO will be active. When high, the SDO pin will output a high-impedance state.

The logic-low level of SDO will match the active-low voltage on CS

SDO - Serial Data Output, Pin 8

SDO is the serial data output. It will output a high-impedance state if CS = 1. The logic-low level of SDO

will match the active-low voltage on CS

SCLK - Serial Clock Input, Pin 5

SCLK is the serial bit-clock which controls the shifting of data from the ADCs. This input goes through a

Schmitt trigger to allow for slow rise and fall time signals. If held high, the device will enter sleep mode.

In the CS5510/12, this input is also used as a master clock source which determines conversion speeds

and throughput. In the CS5511/13, SCLK is only used to read the conversion data and put the part in

sleep mode.

Measurement and Reference Inputs

AIN+, AIN- - Differential Analog Input, Pins 2, 3

Differential input pins into the device

VREF - Voltage Reference Input, Pin 1

Input Voltage which establishes the voltage reference, with respect to V-, for the on-chip modulator

Power Supply Connections

V+ - Positive Power, Pin 6

Positive supply voltage

V- - Negative Supply, Pin 7

Negative supply voltage

VREF

AIN+

AIN-

SDO

V-

V+

SCLK

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

CS5510-ASZ

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Analog to Digital Converters - ADC 16-Bit Delta Sigma ADC Ext. OSC

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CS5510-ASZ

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