MC10E016FNR2G Datasheet MC10E016FNR2G, MC10E016FNG, MC100E016FNG | P7-P9

MC10E016, MC100E016

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APPLICATIONS INFORMATION

Cascading Multiple E016 Devices

For applications which call for larger than 8-bit counters

multiple E016s can be tied together to achieve very wide bit

width counters. The active low terminal count (TC

) output

and count enable input (CE

) greatly facilitate the cascading

of E016 devices. Two E016s can be cascaded without the

need for external gating, however for counters wider than 16

bits external OR gates are necessary for cascade

implementations.

Figure 3 below pictorially illustrates the cascading of 4

E016s to build a 32-bit high frequency counter. Note the

E101 gates used to OR the terminal count outputs of the

lower order E016s to control the counting operation of the

higher order bits. When the terminal count of the preceding

device (or devices) goes low (the counter reaches an all 1s

state) the more significant E016 is set in its count mode and

will count one binary digit upon the next positive clock

transition. In addition, the preceding devices will also count

one bit thus sending their terminal count outputs back to a

high state disabling the count operation of the more

significant counters and placing them back into hold modes.

Therefore, for an E016 in the chain to count, all of the lower

order terminal count outputs must be in the low state. The bit

width of the counter can be increased or decreased by simply

adding or subtracting E016 devices from Figure 3 and

maintaining the logic pattern illustrated in the same figure.

The maximum frequency of operation for the cascaded

counter chain is set by the propagation delay of the TC

output and the necessary setup time of the CE input and the

propagation delay through the OR gate controlling it (for

16-bit counters the limitation is only the TC

propagation

delay and the CE

setup time). Figure 3 shows EL01 gates

used to control the count enable inputs, however, if the

frequency of operation is lower a slower, ECL OR gate can

be used. Using the worst case guarantees for these

parameters from the ECLinPS data book, the maximum

count frequency for a greater than 16-bit counter is 500 MHz

and that for a 16-bit counter is 625 MHz.

Note that this assumes the trace delay between the TC

outputs and the CE inputs are negligible. If this is not the

case estimates of these delays need to be added to the

calculations.

Figure 3. 32-Bit Cascaded E016 Counter

EL01

CLOCK

P0 -> P7

CLK

P0 -> P7

TCCLK

EL01

P0 -> P7

CLK

P0 -> P7

MSB

E016

Q0 -> Q7Q0 -> Q7 Q0 -> Q7

E016

Q0 -> Q7

E016

LSB

E016

LOAD

TCCLK

MC10E016, MC100E016

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APPLICATIONS INFORMATION (continued)

Programmable Divider

The E016 has been designed with a control pin which

makes it ideal for use as an 8-bit programmable divider. The

TCLD pin (load on terminal count) when asserted reloads

the data present at the parallel input pin (Pn’s) upon reaching

terminal count (an all 1s state on the outputs). Because this

feedback is built internal to the chip, the programmable

division operation will run at very nearly the same frequency

as the maximum counting frequency of the device. Figure 4

below illustrates the input conditions necessary for utilizing

the E016 as a programmable divider set up to divide by 113.

HLLLHHHH

TCLD

CLK

P7 P6 P4 P3 P2 P1 P0P5

Q7 Q6 Q4 Q3 Q2 Q1 Q0Q5

Figure 4. Mod 2 to 256 Programmable Divider

To determine what value to load into the device to

accomplish the desired division, the designer simply

subtracts the binary equivalent of the desired divide ratio

from the binary value for 256. As an example for a divide

ratio of 113:

Pn’s = 256 − 113 = 8F

= 1000 1111

where:

P0 = LSB and P7 = MSB

Forcing this input condition as per the setup in Figure 4

will result in the waveforms of Figure 5. Note that the TC

output is used as the divide output and the pulse duration is

equal to a full clock period. For even divide ratios, twice the

desired divide ratio can be loaded into the E016 and the TC

output can feed the clock input of a toggle flip flop to create

a signal divided as desired with a 50% duty cycle.

Table 11. Preset Values for Various Divide Ratios

Divide

Ratio

Preset Data Inputs

P7 P6 P5 P4 P3 P2 P1 P0

2 H H H H H H H L

3 H HHHHHLH

4 H HHHHHL L

5 H HHHHLHH

w w •••••••

w • •••••••

112 H LLHLLLL

113 H L L LHHHH

114 H L L LHHHL

• • •••••••

254 L LLLLLHL

255 L LLLLLLH

256 L L L L L L L L

A single E016 can be used to divide by any ratio from 2

to 256 inclusive. If divide ratios of greater than 256 are

needed multiple E016s can be cascaded in a manner similar

to that already discussed. When E016s are cascaded to build

larger dividers the TCLD pin will no longer provide a means

for loading on terminal count. Because one does not want to

reload the counters until all of the devices in the chain have

reached terminal count, external gating of the TC

pins must

be used for multiple E016 divider chains.

•••

Clock

Load

DIVIDE BY 113

Load1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111

Figure 5. Divide by 113 E016 Programmable Divider Waveforms

MC10E016, MC100E016

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APPLICATIONS INFORMATION (continued)

E016

MSB

CLK TC

PECE

E016

CLK TC

PECE

E016

CLK TC

PECE

EL01

CLOCK

Q0 -> Q7

PO -> P7

Q0 -> Q7

PO -> P7

Q0 -> Q7

PO -> P7

Q0 -> Q7

PO -> P7

E016

LSB

CLK TC

PECE

Figure 6. 32-Bit Cascaded E016 Programmable Divider

OUT

Figure 6 shows a typical block diagram of a 32-bit divider

chain. Once again to maximize the frequency of operation

EL01 OR gates were used. For lower frequency applications

a slower OR gate could replace the EL01. Note that for a

16-bit divider the OR function feeding the PE

(program

enable) input CANNOT be replaced by a wire OR tie as the

output of the least significant E016 must also feed the CE

input of the most significant E016. If the two TC outputs

were OR tied the cascaded count operation would not

operate properly. Because in the cascaded form the PE

feedback is external and requires external gating, the

maximum frequency of operation will be significantly less

than the same operation in a single device.

Maximizing E016 Count Frequency

The E016 device produces 9 fast transitioning

single-ended outputs, thus V

noise can become

significant in situations where all of the outputs switch

simultaneously in the same direction. This V

noise can

negatively impact the maximum frequency of operation of

the device. Since the device does not need to have the Q

outputs terminated to count properly, it is recommended that

if the outputs are not going to be used in the rest of the system

they should be left unterminated. In addition, if only a subset

of the Q outputs are used in the system only those outputs

should be terminated. Not terminating the unused outputs

will not only cut down the V

noise generated but will also

save in total system power dissipation. Following these

guidelines will allow designers to either be more aggressive

in their designs or provide them with an extra margin to the

published data book specifications.

Figure 7. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D

− Termination of ECL Logic Devices)

Driver

Device

Receiver

Device

Q D

= 50 W

50 W 50 W

= V

− 2.0 V

P1-P3 P4-P6 P7-P9 P10-P11

MC10E016FNR2G

Mfr. #:

Buy MC10E016FNR2G

Manufacturer:

ON Semiconductor

Description:

Counter ICs 5V ECL 8-Bit Binary Up Synchronous

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New from this manufacturer.

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MC10E016FNR2G

MC10E016FNR2G

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