REV. A–8–
AD9059
Digital Logic (5 V/3 V Systems)
The digital inputs and outputs of the AD9059 can easily be
configured to interface directly with 3 V or 5 V logic systems.
The encode and power-down (PWRDN) inputs are CMOS
stages with TTL thresholds of 1.5 V, making the inputs compat-
ible with TTL, 5 V CMOS, and 3 V CMOS logic families. As
with all high speed data converters, the encode signal should be
clean and jitter free to prevent degradation of ADC dynamic
performance.
The AD9059’s digital outputs will also interface directly with 5 V
or 3 V CMOS logic systems. The voltage supply pins (V
DD
) for
these CMOS stages are isolated from the analog V
D
voltage
supply. By varying the voltage on these supply pins, the digital
output high levels will change for 5 V or 3 V systems. The V
DD
pins are internally connected on the AD9059 die. Care should
be taken to isolate the V
DD
supply voltages from the 5 V analog
supply to minimize noise coupling into the ADCs.
The AD9059 provides high impedance digital output operation
when the ADC is driven into power-down mode (PWRDN,
logic high). A 200 ns (minimum) power-down time should be
provided before a high impedance characteristic is required. A
200 ns power-up period should be provided to ensure accurate
ADC output data after reactivation (valid output data is avail-
able three clock cycles after the 200 ns delay).
Timing
The AD9059 is guaranteed to operate with conversion rates
from 5 MSPS to 60 MSPS. At 60 MSPS, the ADC is designed
to operate with an encode duty cycle of 50%, but performance
is insensitive to moderate variations. Pulsewidth variations of up
to ± 10% (allowing the encode signal to meet the minimum/
maximum high/low specifications) will cause no degradation in
ADC performance (see Figure 1).
Due to the linked ENCODE architecture of the ADCs, the
AD9059 cannot be operated in a 2-channel ping-pong mode.
Power Dissipation
The power dissipation of the AD9059 is specified to reflect a
typical application setup under the following conditions: encode
is 60 MSPS, analog input is –0.5 dBFS at 10.3 MHz, V
D
is 5 V,
V
DD
is 3 V, and digital outputs are loaded with 7 pF typical
(10 pF maximum). The actual dissipation will vary as these
conditions are modified in user applications. TPC 7 shows typi-
cal power consumption for the AD9059 versus ADC encode
frequency and V
DD
supply voltage.
A power-down function allows users to reduce power dissipation
when ADC data is not required. A TTL/CMOS high signal
(PWRDN) shuts down portions of the dual ADC and brings total
power dissipation to less than 10 mW. The internal band gap
voltage reference remains active during power-down mode to
minimize ADC reactivation time. If the power-down function is
not desired, Pin 3 should be tied to ground. Both ADC channels
are controlled simultaneously by the PWRDN pin; they cannot
be shut down or turned on independently.
Applications
The wide analog bandwidth of the AD9059 makes it attractive for
a variety of high performance receiver and encoder applications.
Figure 4 shows the dual ADC in a typical low cost I and Q
demodulator implementation for cable, satellite, or wireless
LAN modem receivers. The excellent dynamic performance of
the ADC at higher analog input frequencies and encode rates
empowers users to employ direct IF sampling techniques (see
TPC 2). IF sampling eliminates or simplifies analog mixer and
filter stages to reduce total system cost and power.
AD9059
BPF
BPF
90
°
VCO
IF IN
VCO
ADC
ADC
Figure 4. I and Q Digital Receiver
The high sampling rate and analog bandwidth of the AD9059
are ideal for computer RGB video digitizer applications. With a
full-power analog bandwidth of 2× the maximum sampling rate,
the ADC provides sufficient pixel-to-pixel transient settling time
to ensure accurate 60 MSPS video digitization. Figure 5 shows
a typical RGB video digitizer implementation for the AD9059.
8
RED
GREEN
AD9059
BLUE
AD9059
H-SYNC
PLL
PIXEL CLOCK
8
8
ADC
ADC
ADC
ADC
Figure 5. RGB Video Encoder
