LT5572
10
5572f
input (2V
P-P,DIFF
). This maximum RF output level is limited
by the 0.5V
PEAK
maximum baseband swing possible for a
0.5V
DC
common mode voltage level (assuming no extra
negative supply voltage available).
It is possible to bias the LT5572 to a common mode base-
band voltage level other than 0.5V. Table 1 shows the typical
performance for different common mode voltages.
LO section
The internal LO input amplifi er performs single-ended to
differential conversion of the LO input signal. Figure 4
shows the equivalent circuit schematic of the LO input.
The internal, differential LO signal is split into in-phase
and quadrature (90° phase shifted) signals that drive LO
buffer sections. These buffers drive the double balanced I
and Q mixers. The phase relationship between the LO input
and the internal in-phase LO and quadrature LO signals
is fi xed, and is independent of start-up conditions. The
phase shifters are designed to deliver accurate quadrature
signals for an LO frequency near 2GHz. For frequencies
signifi cantly below 1.8GHz or above 2.4GHz, the quadra-
ture accuracy will diminish, causing the image rejection
to degrade. The LO pin input impedance is about 50Ω and
the recommended LO input power is 0dBm. For lower LO
input power, the gain, OIP2, OIP3 and dynamic range will
degrade, especially below –5dBm and at T
A
= 85°C. For
high LO input power (e.g., 5dBm), the LO feedthrough
will increase, without improvement in linearity or gain.
Harmonics present on the LO signal can degrade the
image rejection, because they introduce a small excess
phase shift in the internal phase splitter. For the second (at
4GHz) and third harmonics (at 6GHz) at –20dBc level, the
introduced signal at the image frequency is about –57dBc
or lower, corresponding to an excess phase shift much
less than 1 degree. For the second and third harmonics at
–10dBc, still the introduced signal at the image frequency
is about –47dBc. Higher harmonics than the third will have
less impact. The LO return loss typically will be better than
14dB over the 1.7GHz to 2.4GHz range. Table 2 shows the
LO port input impedance vs frequency.
Table 2. LO Port Input Impedance vs Frequency for EN = High
and P
LO
= 0dBm
FREQUENCY INPUT IMPEDANCE
S
11
(MHz) (Ω)
Mag Angle
1000 45.9+j15.7 0.167 95
1400 60.8+j2.1 0.099 9.4
1600 63.2-j6.0 0.128 –22
1800 61.8-j14.2 0.163 –44
2000 56.4-j16.8 0.165 –61
2200 51.7-j14.7 0.144 –75
2400 47.3-j11.3 0.119 –97
2600 42.5-j8.6 0.122 –126
The input impedance of the LO port is different if the part
is in shutdown mode. The LO input impedance for EN =
Low is given in Table 3.
Table 1. Typical Performance Characteristics vs V
CM
for f
LO
= 2GHz, P
LO
= 0dBm
V
CM
(V) I
CC
(mA) G
V
(dB) OP1dB (dBm) OIP2 (dBm) OIP3 (dBm) NFloor (dBm/Hz) LOFT (dBm) IR (dBc)
0.1 77 –1.3 0.0 47 8.3 –163.2 –45.6 –42.2
0.2 89 –2.7 4.7 45 11.4 –162.2 –42.6 –36.2
0.3 101 –2.1 7.1 49 15.0 –160.9 –42.0 –37.0
0.4 113 –2.0 8.6 51 18.2 –160.2 –42.4 –39.3
0.5 126 –1.9 9.3 52 21.2 –159.2 –42.4 –41.5
0.6 138 –1.9 9.1 52 21.1 –158.6 –42.1 –44.4
APPLICATIO S I FOR ATIO
WUU
U
V
CC
20pF
LO
INPUT
Z
IN
56
5572 F04
Figure 4. Equivalent Circuit Schematic of the LO Input
LT5572
11
5572f
Table 3. LO Port Input Impedance vs Frequency for EN = Low
and P
LO
= 0dBm
FREQUENCY INPUT IMPEDANCE
S
11
(MHz) (Ω)
Mag Angle
1000 51.2+j45.6 0.409 64
1400 133-j11.8 0.456 –4.5
1600 97.8-j65.8 0.502 –30
1800 58.6-j67.8 0.534 –51
2000 39.0-j55.6 0.540 –69
2200 29.6-j43.2 0.527 –87
2400 23.7-j30.8 0.506 –108
2600 19.7-j20.5 0.503 –130
RF Section
After up-conversion, the RF outputs of the I and Q mixers are
combined. An on-chip balun performs internal differential
to single-ended output conversion, while transforming the
output signal impedance to 50Ω. Table 4 shows the RF
port output impedance vs frequency.
Table 4. RF Port Output Impedance vs Frequency for EN = High
and P
LO
= 0dBm
FREQUENCY OUTPUT IMPEDANCE
S
22
(MHz) (Ω)
Mag Angle
1000 20.7+j9.9 0.434 153
1400 32.2+j20.3 0.319 117
1600 44.9+j21.8 0.230 90
1800 56.4+j12.2 0.129 56
2000 52.6+j0.5 0.025 10
2200 43.0+j0.5 0.075 176
2400 36.8+j5.6 0.164 153
2600 32.9+j11.0 0.243 140
The RF output S
22
with no LO power applied is given in
Table 5.
Table 5. RF Port Output Impedance vs Frequency for EN = High
and No LO Power Applied
FREQUENCY OUTPUT IMPEDANCE
S
22
(MHz) (Ω)
Mag Angle
1000 21.2+j10.1 0.424 153
1400 35.3+j18.4 0.270 117
1600 46.1+j14.1 0.150 97
1800 47.4+j5.0 0.057 114
2000 42.0+j3.0 0.093 157
2200 37.5+j6.8 0.162 147
2400 34.8+j11.8 0.224 134
2600 32.8+j16.1 0.279 126
For EN = Low the S
22
is given in Table 6.
Table 6. RF Port Output Impedance vs Frequency for EN = Low
FREQUENCY OUTPUT IMPEDANCE
S
22
(MHz) (Ω)
Mag Angle
1000 20.3+j9.7 0.440 154
1400 30.6+j20.2 0.338 120
1600 41.8+j23.6 0.264 95
1800 55.6+j18.5 0.181 63
2000 58.3+j49.1 0.089 28
2200 48.8-j0.1 0.012 -172
2400 40.4+j3.1 0.112 160
2600 34.7+j8.3 0.205 146
To improve S
22
for lower frequencies, a shunt capacitor
can be added to the RF output. At higher frequencies, a
shunt inductor can improve the S
22
. Figure 5 shows the
equivalent circuit schematic of the RF output.
Note that an ESD diode is connected internally from
the RF output to ground. For strong output RF signal
levels (higher than 3dBm) this ESD diode can degrade
the linearity performance if the 50Ω termination imped-
ance is connected directly to ground. To prevent this, a
coupling capacitor can be inserted in the RF output line.
This is strongly recommended for 1dB compression
measurements.
APPLICATIO S I FOR ATIO
WUU
U
20pF
V
CC
2.1pF52.5
RF
OUTPUT
3nH
5572 F05
Figure 5. Equivalent Circuit Schematic of the RF Output
Enable Interface
Figure 6 shows a simplifi ed schematic of the EN pin
interface. The voltage necessary to turn on the LT5572
is 1V. To disable (shut down) the chip, the enable voltage
must be below 0.5V. If the EN pin is not connected, the
chip is disabled. This EN = Low condition is guaranteed
by the 75k on-chip pull-down resistor. It is important
that the voltage at the EN pin does not exceed V
CC
by
more than 0.5V. If this should occur, the full-chip supply
LT5572
12
5572f
APPLICATIO S I FOR ATIO
WUU
U
EN
V
CC
75k
5572 F06
25k
Figure 6. EN Pin Interface
BBIPBBIM
J1
16 15
R5
49.9
R1
100
V
CC
EN
LO IN
R2
49.9
14 13
V
CC
9
10
11
12
4
3
2
1
5678
5572 F07
17
R3
49.9
C2
100nF
C1
100nF
RF
OUT
BBQM
BBQP
BOARD NUMBER: DC945A
J6
J3
J4
J5
R4
49.9
J2
BBMI
LT5572
BBPI V
CC
BBMQ GND
GND
BBPQ V
CC
GND
GND
RF
GND
GND
LO
GND
EN
GND
Figure 7. Evaluation Circuit Schematic
Figure 8. Component Side of Evaluation Board
Figure 9. Bottom Side of Evaluation Board
current could be sourced through the EN pin ESD pro-
tection diodes, which are not designed for this purpose.
Damage to the chip may result.
Evaluation Board
Figure 7 shows the evaluation board schematic. A good
ground connection is required for the Exposed Pad. If this
is not done properly, the RF performance will degrade.
Additionally, the Exposed Pad provides heat sinking for
the part and minimizes the possibility of the chip over-
heating. R1 (optional) limits the EN pin current in the
event that the EN pin is pulled high while the V
CC
inputs
are low. The application board PCB layouts are shown in
Figures 8 and 9.

LT5572EUF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Modulator / Demodulator 2GHz Direct Quadrature Modulator w/ HiZ & 0.5V Bias
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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