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87993AYILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
1-to-5 Differential-to-3.3V LVPECL
PLL Clock Driver W/Dynamic Clock Switch
87993I
DATASHEET
87993I REVISION C 2/18/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 87993I is a PLL clock driver designed specifi cally for re-
dundant clock tree designs. The device receives two differential
LVPECL clock signals from which it generates 5 new differential
LVPECL clock outputs. Two of the output pairs regenerate the
input signal frequency and phase while the other three pairs
generate 2x, phase aligned clock outputs. External PLL feed-
back is used to also provide zero delay buffer performance.
The 87993I Dynamic Clock Switch (DCS) circuit continuously
monitors both input CLK signals. Upon detection of a failure
(CLK stuck HIGH or LOW for at least 1 period), the INP_BAD
for that CLK will be latched (H). If that CLK is the primary clock,
the DCS will switch to the good secondary clock and phase/
frequency alignment will occur with minimal output phase
disturbance. The typical phase bump caused by a failed clock
is eliminated.
FEATURES
• Five differential 3.3V LVPECL outputs
• Selectable differential clock inputs
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 50MHz to 250MHz
• VCO range: 200MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with confi gurable frequencies
• Cycle-to-cycle jitter (RMS): 20ps (maximum)
• Output skew: 70ps (maximum), within one bank
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
• Pin compatible with MPC993
32-Lead QFP (LQFP)
7mm x 7mm x 1.4mm
package body
Y Package
Top View
24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
V
CC
INP0BAD
INP1BAD
CLK_SELECTED
V
EE
nEXT_FB
EXT_FB
V
EE
nQA1
QA1
nQA0
QA0
V
CC
VCCA
MAN_OVERRIDE
PLL_SEL
VEE
nCLK1
CLK1
CLK_SEL
nCLK0
CLK0
nALARM_RESET
nMR
V
CC
nQB2
QB2
nQB1
QB1
nQB0
QB0
V
CC
87993I
PIN ASSIGNMENT
BLOCK DIAGRAM
PLL
÷2
÷4
Dynamic Switch
Logic
nQB0
QB0
nQB1
QB1
nQB2
QB2
nQA0
QA0
nQA1
QA1
PLL_SEL
CLK_SELECTED
INP1BAD
INP0BAD
MAN_OVERRIDE
ALARM_RESET
SEL_CLK
nCLK0
CLK0
nCLK1
CLK1
nEXT_FB
EXT_FB
nMR
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
87993I DATA SHEET
2 REVISION C 2/18/15
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1 nMR Input Pullup
Active LOW Master Reset. When logic LOW, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic HIGH, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
2 nALARM_RESET Input Pullup
When LOW, resets the input bad fl ags and aligns CLK_SELECTED with
SEL_CLK. LVCMOS / LVTTL interface levels.
3 CLK0 Input Pulldown Non-inverting differential clock input.
4 nCLK0 Input Pullup Inverting differential clock input.
5 SEL_CLK Input Pulldown
Clock select input. When LOW, selects CLK0, nCLK0 inputs. When
HIGH, selects CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels.
6 CLK1 Input Pulldown Non-inverting differential clock input.
7 nCLK1 Input Pullup Inverting differential clock input.
8, 9, 12 V
EE
Power Negative supply pins.
10 EXT_FB Input Pulldown Differential external feedback.
11 nEXT_FB Input Pullup Differential external feedback.
13 CLK_SELECTED Output
LOW, when CLK0, nCLK0 is selected, HIGH, when CLK1, nCLK1
is selected. LVCMOS / LVTTL interface levels.
14 INP1BAD Output
Indicates detection of a bad input reference clock 1 with respect to the
feedback signal. The output is active HIGH and will remain HIGH until the
alarm reset is asserted.
15 INP0BAD Output
Indicates detection of a bad input reference clock 0 with respect to the
feedback signal. The output is active HIGH and will remain HIGH until the
alarm reset is asserted.
16, 17, 24,
29
V
CC
Power Core supply pins.
18, 19 nQB2, QB2 Output Differential output pair. LVPECL interface levels.
20, 21 nQB1, QB1 Output Differential output pair. LVPECL interface levels.
22, 23 nQB0, QB0 Output Differential output pair. LVPECL interface levels.
25, 26 nQA1, QA1 Output Differential output pair. LVPECL interface levels.
27, 28 nQA0, QA0 Output Differential output pair. LVPECL interface levels.
30 V
CCA
Power Analog supply pin.
31 MAN_OVERRIDE Input Pulldown
Manual override. When HIGH, disables internal clock switch circuitry.
LVCMOS / LVTTL interface levels.
32 PLL_SEL Input Pullup
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock.When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
KΩ
R
PULLDOWN
Input Pulldown Resistor 51
KΩ
REVISION C 2/18/15
87993I DATA SHEET
3 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, V
CC
= V
CCA
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= V
CCA
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Core Supply Voltage 3.135 3.3 3.465 V
V
CCA
Analog Supply Voltage 3.135 3.3 3.465 V
I
EE
Power Supply Current 80 180 mA
I
CCA
Analog Supply Current 15 20 mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, V
CC
= V
CCA
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage LVCMOS Inputs 2 3.3 V
V
IL
Input Low Voltage LVCMOS Inputs -0.3 0.8 V
I
IH
Input High Current
SEL_CLK, MAN_
OVERRIDE
V
IN
= V
CC
= 3.465V 5 µA
nALARM_RESET,
PLL_SEL, nMR
V
IN
= V
CC
= 3.465V 120 µA
I
IL
Input Low Current
SEL_CLK, MAN_
OVERRIDE
V
IN
= 0V, V
CC
= 3.465V -5 µA
nALARM_RESET,
PLL_SEL, nMR
V
IN
= 0V, V
CC
= 3.465V -120 µA
V
OH
Output High Voltage; NOTE 1 2.4
V
V
OL
Output Low Voltage; NOTE 1 0.5
V
NOTE 1: Outputs terminated with 50Ω to V
CC
/2. See Parameter Measurement Information Section,
“3.3V Output Load AC Test Circuit diagram”.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK0, CLK1, EXT_
FB
V
IN
= V
CC
= 3.465V 5 µA
nCLK0, nCLK1,
nEXT_FB
V
IN
= V
CC
= 3.465V 120 µA
I
IL
Input Low Current
CLK0, CLK1, EXT_
FB
V
IN
= 0V, V
CC
= 3.465V -5 µA
nCLK0, nCLK1,
nEXT_FB
V
IN
= 0V, V
CC
= 3.465V -120 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage; NOTE 1, 2 V
EE
+ 0.5 V
CC
- 0.85 V
NOTE 1: Common mode voltage is defi ned as V
IH
.
NOTE 2: For single ended appliations, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

87993AYILF

Mfr. #:
Buy 87993AYILF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 5 LVPECL OUT CLOCK GENERATOR
Lifecycle:
New from this manufacturer.
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