1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
87993I DATA SHEET
8 REVISION C 2/18/15
FIGURE 4C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet
the V
PP
and V
CMR
input requirements. Figures 4A to 4D show
interface examples for the CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
FIGURE 4A. CLK/nCLK INPUT DRIVEN BY
IDT’S LVHSTL DRIVER
examples only. Please consult with the vendor of the driver
component to confi rm the driver termination requirements. For
example in Figure 4A, the input termination applies for IDT’s
LVHSTL drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
